A video pipeline passes pixels from a camera interface to a scaler, then a colour converter, then an encoder. Nobody reads or writes an address; data simply flows from one block to the next, a packet per video line. Using AXI4 would mean inventing addresses nobody needs. AXI-Stream keeps AXI's handshake and throws away everything about memory.
How does AXI-Stream answer each question when there is no address and no response?
Constraint | AXI-Stream |
|---|---|
C1 Distance and medium | On-chip wires |
C2 Bandwidth and latency | High, steady throughput: one beat per cycle |
C3 Wires | Data plus a few sideband signals |
C4 Topology | Point-to-point between processing stages, sometimes through stream switches |
C5 Who builds each side | Many IP vendors; Arm specification (IHI 0051) |
Each answer links to the lesson that explains the idea behind it.
# | Question | Answer |
|---|---|---|
1 | When is the data valid? | A common clock, ACLK (1.1) |
2 | Where does a message start and end? | TLAST marks the last transfer of a packet; TKEEP marks null bytes (fact A9) (2.2) |
3 | Is the receiver ready? | TVALID/TREADY with AXI's rules (fact A10) (3.3) |
4 | How much may I send before I hear back? | TREADY back-pressure, hop by hop (4.1) |
5 | What exactly is being asked? | No addresses, reads or writes: a one-way stream with TID, TDEST and TUSER sideband (fact A32) (0.8) |
6 | How many requests can be in flight? | One beat per cycle; nothing is outstanding because nothing is answered (6.1) |
7 | In what order do results become visible? | In order within a stream; different streams may be interleaved (fact A32) (6.7) |
8 | Who gets the wire? | Switches arbitrate between streams, usually at packet boundaries so packets stay contiguous (8.5) |
9 | Why can it hang? | No request/response dependencies, but a loop of stages with finite buffers, or a sink waiting for a whole packet that cannot arrive, can still deadlock (9.2) |
10 | What if bits go wrong? | Not addressed: no error signalling; systems use TUSER or higher layers |
11 | How do the two sides agree at start-up? | None: reset rules as AXI |
12 | How do we save power without losing data? | Not addressed by the protocol |
13 | What if there are several copies of one value? | Not applicable: no shared memory |
14 | Who is allowed to ask? | Not addressed: no protection attributes |
15 | How do we know it is correct? | Arm protocol assertions (fact A29); monitors framing packets by TLAST (15.4) |
Handshake only: the valid/ready rules are the whole protocol; everything else is optional sideband.
Packets by TLAST: framing is a single bit, not a length field.
Sideband identity: TID and TDEST replace addresses for routing and stream identity.
A packet switch (illustrative) arbitrated between two sources on every beat, interleaving their packets, while the downstream block assumed each packet arrived contiguously. Mixed packets corrupted frames. Either the switch arbitrates only at TLAST boundaries, or every stage must handle interleaving by TID; the choice must be stated in the design's interface contract.
The transfer with TLAST high is the packet's last.
There is no response channel; errors must travel forward in TUSER or be handled at a higher layer.
AXI-Stream: AXI's handshake, no addresses or responses, packets by TLAST.
TID, TDEST and TUSER give stream identity, routing and sideband; TKEEP marks null bytes.
State interleaving and sideband meaning in each stream's contract.