A chip has forty peripheral blocks (timers, GPIO, UART controllers), each with a handful of registers that software reads and writes a few times per second. Connecting each to a high-performance bus would waste area and power on bandwidth nobody uses. APB is what remains when you strip a bus down to a register access: address, select, enable, data, ready, error.
How does APB answer each question, and why is so little needed for register access?
Constraint | APB |
|---|---|
C1 Distance and medium | On-chip wires, usually behind a bridge from a faster bus |
C2 Bandwidth and latency | Low; at least two cycles per transfer |
C3 Wires | Parallel address, data and a few control signals; area matters more than wire count |
C4 Topology | One requester (the bridge) and many completers, selected by PSEL |
C5 Who builds each side | Many IP vendors; one Arm specification |
Each answer links to the lesson that explains the idea behind it.
# | Question | Answer |
|---|---|---|
1 | When is the data valid? | A common clock (PCLK); signals are sampled on its rising edge (1.1) |
2 | Where does a message start and end? | Each transfer is a SETUP cycle then an ACCESS phase, marked by PSEL and PENABLE (fact A8) (2.2) |
3 | Is the receiver ready? | The completer stretches ACCESS by holding PREADY low: a wait state (3.2) |
4 | How much may I send before I hear back? | Implicit: one transfer at a time, paced by PREADY (4.1) |
5 | What exactly is being asked? | Single reads and writes; no bursts; APB4 adds byte strobes (PSTRB) and protection (PPROT) (fact A17) (5.1) |
6 | How many requests can be in flight? | Exactly one transfer outstanding (6.3) |
7 | In what order do results become visible? | Trivially in order: one at a time (7.1) |
8 | Who gets the wire? | No arbitration: a single requester selects one completer with PSEL (8.1) |
9 | Why can it hang? | A completer that never raises PREADY hangs the bus; systems add timeouts in the bridge (9.9) |
10 | What if bits go wrong? | PSLVERR reports a failed transfer (APB3); no detection or retry of bit errors (10.7) |
11 | How do the two sides agree at start-up? | None: a fixed address map in the bridge |
12 | How do we save power without losing data? | Not addressed by the protocol; idle completers see no activity, and clock gating is done by the system |
13 | What if there are several copies of one value? | Not applicable: registers are not cached coherently |
14 | Who is allowed to ask? | PPROT carries privilege and secure attributes (APB4) for completers or firewalls to check (14.1) |
15 | How do we know it is correct? | Arm protocol checks and simple VIP; tests cover wait states, errors and back-to-back transfers (15.3) |
Two-phase transfer: a one-cycle setup gives decoders and completers time, keeping their logic slow and small.
One at a time: no pipelining, no outstanding transfers, no ordering problems.
Behind a bridge: high-performance buses carry APB traffic to a bridge, so the many slow peripherals never load the fast bus.
A peripheral (illustrative) held PREADY low while waiting for a slow internal clock domain to answer, and that domain had been clock-gated. The APB bridge waited for ever, and with it the processor's load instruction. Adding a timeout in the bridge that completed the transfer with PSLVERR turned the hang into a reported error, and the driver now enables the peripheral's clock before touching it.
Two: one setup cycle and one access cycle with PREADY high.
Only one transfer is ever in flight.
APB: setup then access, stretched by PREADY, one transfer at a time.
It suits many small, slow register blocks where area and power matter more than bandwidth.
Its one liveness risk is a completer that never raises PREADY; bridges add timeouts.