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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
    • How to Dissect a Protocol
    • UART
    • SPI
    • I2C
    • APB
    • AHB
    • AXI4
    • AXI-Stream
    • PCI Express
    • DDR
    • CHI
    • Ethernet
    • USB
    • UCIe
    • CXL
    • Protocols Compared: Protocols Dissected
    • Drills: Protocols Dissected
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
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‹Part 16: Protocols Dissected
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 16: Protocols Dissected
  4. UCIe

Part 16 · Protocols Dissected · Principal (P)

UCIe

UCIe dissected through the twenty questions: a die-to-die interconnect for chiplets that carries existing protocols (PCIe, CXL or raw streams) over a very short, very wide, forwarded-clock link, with a die-to-die adapter adding CRC, retry and arbitration. Which questions it answers itself, and which it inherits.

On this page

    Note

    Level: Principal (P) · Answers: How do real protocols answer the fifteen questions?

    Before this: PCI Express, Flits, Phits and Packing

    A processor is built from four dies in one package: two compute dies, an I/O die and a memory controller die, possibly from different teams or vendors. They are millimetres apart, connected by thousands of tiny bumps. Running a full PCI Express physical layer, designed for lossy boards and connectors, across that gap would waste power and area. UCIe keeps the protocols everyone already uses and replaces only what the short distance makes unnecessary.

    How does UCIe answer each question, and which answers does it borrow from the protocols it carries?

    Constraints first: what UCIe had to work with

    Constraint

    UCIe

    C1 Distance and medium

    Millimetres inside a package: organic substrate (standard) or silicon interposer or bridge (advanced) (fact P39)

    C2 Bandwidth and latency

    Very high bandwidth density and low latency, at low energy per bit

    C3 Wires

    Many short, parallel lanes; bumps are plentiful compared with board pins

    C4 Topology

    Point-to-point between dies in a package

    C5 Who builds each side

    Different dies, possibly different vendors; a standard so chiplets can be combined

    Compared with PCI Express, the protocol layer is reused unchanged and the physical layer is replaced by a short-reach one; the die-to-die adapter keeps the link reliable.

    UCIe's answers to the fifteen questions

    Each answer links to the lesson that explains the idea behind it.

    #

    Question

    Answer

    1

    When is the data valid?

    A clock forwarded alongside the data lanes, practical over millimetres (fact P39) (1.3)

    2

    Where does a message start and end?

    Flits: PCIe and CXL traffic in 68-byte or 256-byte flit formats (fact P39) (2.10)

    3

    Is the receiver ready?

    Inherited from the carried protocol: PCIe and CXL use credits (4.3)

    4

    How much may I send before I hear back?

    The carried protocol's credits (4.6)

    5

    What exactly is being asked?

    Inherited: PCIe or CXL transactions, or a raw streaming mode (fact P39) (5.17)

    6

    How many requests can be in flight?

    Inherited from the carried protocol

    7

    In what order do results become visible?

    Inherited from the carried protocol (for example PCIe's ordering table)

    8

    Who gets the wire?

    The die-to-die adapter arbitrates when several protocols share one link (fact P39) (8.2)

    9

    Why can it hang?

    Inherited from the carried protocol's deadlock rules, such as PCIe's passing rules (9.4)

    10

    What if bits go wrong?

    CRC and retry in the die-to-die adapter (fact P39) (10.11)

    11

    How do the two sides agree at start-up?

    Link initialisation trains the physical layer and negotiates the protocol and flit format (fact P39) (11.5)

    12

    How do we save power without losing data?

    Low-power link states (L1, L2) in the link state machine (fact P39) (12.2)

    13

    What if there are several copies of one value?

    Inherited: CXL.cache carried over UCIe provides coherence

    14

    Who is allowed to ask?

    Inherited from the carried protocol

    15

    How do we know it is correct?

    Verified against the specification and the carried protocol's VIP; the point of a standard is that chiplets from different sources interoperate (15.8)

    The choices that define UCIe

    • Reuse above, replace below: keep PCIe and CXL transactions, credits and ordering; replace the long-reach physical layer with a short, wide, forwarded-clock one.

    • An adapter for reliability and sharing: CRC, retry and arbitration between protocols sit in one die-to-die layer.

    • Most answers inherited: of the fifteen questions, UCIe itself answers mainly timing, framing, sharing, reliability, bring-up and power.

    What breaks

    A chiplet design (illustrative) assumed that a link millimetres long would never see bit errors and disabled retry to save latency. Under temperature and voltage variation across the package, rare CRC failures appeared; without retry, each one became a fatal link error. Re-enabling the adapter's retry turned them into a few nanoseconds of replay. Short reach lowers the error rate; it does not remove it.

    Why this matters

    Principal lens. UCIe is a lesson in layering: when only the distance changes, replace only the layer that depends on distance. When dissecting it, the inherited answers matter as much as its own: a UCIe link carrying CXL has CXL's ordering, coherence and deadlock rules. Review the adapter's retry, the negotiated mode, and which protocol each traffic class really uses.

    Interview

    Asked: "Why doesn't UCIe just use the PCIe physical layer between chiplets?"

    Weak answer: PCIe is too slow.

    Strong answer: Because the PCIe physical layer is built for lossy boards, connectors and cables: embedded clocks, clock recovery, heavy equalisation and long training, all of which cost power and area per bit. Between dies a few millimetres apart, with thousands of bumps available, a wide parallel link with a forwarded clock is far cheaper per bit and lower latency. So UCIe keeps PCIe and CXL above, their transactions, credits and ordering, adds a die-to-die adapter for CRC, retry and arbitration, and replaces only the physical layer.

    Follow-ups: (1) Which of the fifteen answers does UCIe inherit? (2) Why keep retry on such a short link?

    Check yourself UCIe carries CXL between two dies. Where do its ordering rules come from?

    From CXL, the carried protocol; UCIe does not define its own.

    Check yourself Why is a forwarded clock reasonable for UCIe but not for long PCIe links?

    Over millimetres, skew between the clock and data lanes is small; over boards and cables it is not, so the clock must be embedded and recovered.

    Key takeaways

    • UCIe carries PCIe, CXL or streams between dies, replacing only the distance-dependent physical layer.

    • A die-to-die adapter adds CRC, retry, arbitration and link management.

    • Most of its answers are inherited from the protocol it carries.

    Keep going

    Next: Lesson 16.15, CXL. Three protocols on one PCIe link: I/O, caching and memory.

    Related topics

    • Part 16 overview: Protocols Dissected

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    See also

    • How to Dissect a Protocol
    • UART
    • SPI