A laptop's wireless card is idle for 100 microseconds between packets, and for whole seconds while the user reads. One low-power state cannot suit both. A light state that wakes almost instantly saves a little in the short gaps; a deep state that turns off the clocks and the receiver saves much more but takes far longer to leave, so it only suits the long ones. Every serious link offers several states, arranged as a ladder.
What low-power states can a link offer, and what does each one cost to leave?
The obvious design has two states, on and off. "Off" saves the most, but leaving it means powering up, relocking clock recovery and retraining (lesson 11.4): far too slow for a gap between packets. A single light state wakes quickly but leaves too much running during long idle periods. The answer is a ladder: each step down turns off more, saves more, and takes longer to come back.
Rung | What is turned off | Power | Exit latency | Suits |
|---|---|---|---|---|
Active | Nothing | Full | — | Traffic |
Light idle | Transmitter drives a quiet level; clock recovery kept locked | Somewhat lower | Nanoseconds to around a microsecond | Gaps between packets |
Deeper idle | Transmitters and receivers off; PLLs may stay on | Much lower | Microseconds; may need a short retrain | Gaps between bursts |
Deepest idle | Reference clock and most analogue circuits off | Very low | Tens of microseconds or more | Long idle periods |
Off | Power removed | Zero | Full power-up, training and enumeration | Unused devices |
A device power state says how much of the device is working (fully on, with clocks gated, or powered off with its context lost). A link power state says what the wires are doing. They are related but separate: a fully working device can let its link sleep between packets, and a device being put to sleep must first take its link down in an orderly way (lessons 12.4 and 12.5).
Protocol | States |
|---|---|
PCI Express | Device states D0 to D3hot and D3cold; link states L0, L0s, L1 (with substates L1.1 and L1.2), L2 and L3. ASPM moves an idle link into L0s or L1 while the device stays in D0; each state's exit latency is reported and checked by software before it is enabled. |
USB 3.x | U0 active, U1 and U2 progressively deeper with longer exit latency, U3 suspend. |
Energy-Efficient Ethernet | Low Power Idle with periodic refresh signals. |
DCLink | One sleep state, entered by the step 11 handshake. |
A platform (illustrative) enabled the deepest link substate on every device to pass a battery-life test. An audio device, whose buffer covered only a short time, could not tolerate the exit latency: each wake took longer than its buffer lasted, and playback crackled. The fix was to respect each device's reported latency tolerance and keep that link in a lighter state (lesson 12.6).
More is turned off: receivers, PLLs or clocks must restart and the link must relock or retrain before data can flow.
Yes: a working device's link can sleep between packets (in PCIe, ASPM moves the link to L0s or L1 while the device stays in D0).
Links offer a ladder of states: each deeper rung saves more power and takes longer to leave.
Deep states are left through relocking or retraining, which sets their exit latency.
Link states and device states are separate; check exit latency against each device's tolerance.