Read across for one protocol; read down to see how differently the same power problem is handled.
PCI Express | USB 3.x | Energy-Efficient Ethernet | AMBA (Q/P-Channel) | DCLink | |
|---|---|---|---|---|---|
Idle detection | ASPM hardware timers | Inactivity timers for U1, U2 | PHY enters LPI when idle | Controller decides; device shows activity (QACTIVE, PACTIVE) | Power controller decides |
States | L0, L0s, L1 (L1.1, L1.2), L2, L3; D0 to D3cold | U0, U1, U2, U3 | Active, Low Power Idle | Clock gated or off (Q); several PSTATEs (P) | Awake, asleep |
Entry handshake | Negotiated between link ends; device states set by software | Link-level entry handshake | Signalled between PHYs | Request, accept or deny | slp_req, slp_acc or slp_deny |
Draining | Transactions Pending bit before FLR or power-down | Host stops scheduling transfers | Packets wait for wake | Device accepts only when idle | Accept only with nothing outstanding |
Wake | WAKE# or beacon from deep states; LTR budgets latency | Remote wake-up if enabled | Leave LPI on demand within the PHY's wake time | Withdraw request; QACTIVE asks for wake | Drop slp_req |
Every protocol has a ladder, from a fast-exit light state to near-off.
Off-chip links negotiate entry between the two ends; on-chip power domains use a controller with a request it can be refused.
Wake needs a path that works while asleep, and its latency must be budgeted against devices' tolerance.