A memory interface must move data at well over a gigabit per second per pin across a few centimetres of board. A common clock cannot do it: the flight time alone is a large part of a bit. Yet the same board carries the same signals at those rates every day.
How do you capture data reliably when the trip across the board takes longer than the data stays valid?
The common-clock budget puts the full flight time inside the clock period (lesson 1.1). The natural first fix is to make the trip shorter or the clock slower, and neither scales: chips cannot move closer, and slower clocks defeat the purpose. A cleverer fix is to delay the receiver's clock by the flight time so it lines up with the arriving data. That works for one board at one temperature, but flight time varies with board, load and temperature, and the receiver has no way to know by how much.
Instead of guessing the delay, make the timing reference suffer the same delay as the data. The transmitter sends a clock or a strobe on a wire routed right next to the data wires. Whatever the board does to the data, it does almost the same to the strobe, so at the receiver they arrive together. The flight time drops out of the budget; only the mismatch between the strobe wire and the data wires remains, and careful routing keeps that small. This is a source-synchronous interface: the source sends its own clock.
Two refinements follow:
Double data rate (DDR). Data changes on both edges of the strobe, so each strobe cycle carries two bits per wire. The strobe toggles only as fast as one bit per edge, which halves its frequency for a given data rate.
Edge-aligned or centre-aligned. If the data changes at the same moment as the strobe edges (edge-aligned), the receiver cannot sample on those edges: it would catch data in transition. It must shift the strobe by a quarter of its period (90 degrees), so each edge lands in the middle of a bit. If the transmitter already places the strobe edges in the middle of the bits (centre-aligned), the receiver can use them directly.
The testbench sends six bytes on dq, changing on both edges of dqs (edge-aligned, as a memory does on reads). The receiver delays the strobe by a quarter of its period to make dqs_90, and captures dq on both of its edges. The waveform is sampled with a fast 5 ns clock so the quarter-period shift is visible; that clock is for viewing only and plays no part in the capture.
`timescale 1ns/100ps
// Source-synchronous double data rate: the transmitter sends a strobe (dqs) with the
// data (dq), and dq changes on both edges of dqs. As sent, dq is edge-aligned with dqs:
// it changes exactly when dqs does, so dqs cannot sample it directly. The receiver
// delays the strobe by a quarter of its period (dqs_90), which puts each strobe edge in
// the middle of a data bit, and captures dq on both edges of the delayed strobe.
// The waveform is sampled with a fast clock (5 ns) so the quarter-period shift is visible.
module tb;
localparam real T = 40.0; // strobe period: one data bit every T/2 = 20 ns
logic sclk = 0; // sampling clock for the waveform only
always #2.5 sclk = ~sclk;
logic dqs = 0;
wire dqs_90;
logic [7:0] dq = 8'h00;
logic [7:0] tx [0:5] = '{8'h11, 8'h22, 8'h33, 8'h44, 8'h55, 8'h66};
// Transmitter: strobe and data change together (edge-aligned).
initial begin
#20;
for (int i = 0; i < 6; i++) begin
dq = tx[i]; dqs = ~dqs;
#(T/2);
end
dq = 8'h00;
end
// Receiver: delay the strobe by a quarter period (90 degrees).
assign #(T/4) dqs_90 = dqs;
// Capture on both edges of the delayed strobe, once the transmitter has started
// (the delayed wire's settling from X at time zero is not a strobe edge).
logic armed = 0;
initial @(posedge dqs) armed = 1;
logic [7:0] rx [0:5]; int n = 0;
always @(dqs_90) if (armed && n < 6) begin rx[n] = dq; n++; end
initial begin
$dumpfile("wave.vcd"); $dumpvars(0, tb);
#200;
for (int i = 0; i < 6; i++) if (rx[i] !== tx[i]) begin
$display("FAIL: word %0d captured %h, sent %h", i, rx[i], tx[i]); $finish;
end
$display("PASS: six words captured mid-bit on both edges of the delayed strobe");
$finish;
end
endmoduleHow to read it, slot by slot:
Slot 1: dqs rises and dq changes to 11 at the same moment: edge-aligned. Sampling on this edge would catch the transition.
Slot 3: dqs_90 rises, a quarter period (10 ns, two slots) later, in the middle of the four slots that carry 11. The receiver captures 11 here.
Slot 5: dqs falls and dq changes to 22; slot 7: dqs_90 falls in the middle of 22, and the receiver captures it on this falling edge. Both edges carry data: double data rate.
Slots 9 to 23: the pattern repeats for 33 to 66. Every capture edge sits two slots from the nearest data change on either side, the most margin the bit allows.
With illustrative numbers, compare the two schemes for a link carrying 1.6 Gb/s per pin (625 ps per bit) over 50 mm of trace:
Common clock: flight time alone = 50 mm x 6.7 ps/mm = 335 ps, more than half of the 625 ps bit
Source-synchronous: flight time cancels; what remains is strobe-to-data mismatch,
for example 15 ps of length mismatch + 20 ps of uncertainty in the 90° delay
= 35 ps out of 625 psThe cost is one strobe per group of data wires, and the group must be routed together and kept short enough that the wires really do see the same delay. That is why memory interfaces group their data lines, each group with its own strobe.
Choice | What it costs | When it wins |
|---|---|---|
Edge-aligned strobe (receiver shifts it) | A precise delay element at the receiver | When the transmitter is simple and the receiver is the smarter side (memory reads: the controller shifts) |
Centre-aligned strobe (transmitter shifts it) | A precise shift at the transmitter | When the receiver is simple (memory writes: the memory device just samples) |
Single data rate | Strobe toggles as fast as the data | Lower rates; simpler capture |
Double data rate | Capture on both edges; duty cycle matters | High rates: two bits per strobe cycle |
One strobe per data group | A wire per group; routing rules | Wide buses where one strobe cannot match all wires |
Protocol | Its choice |
|---|---|
DDR memory | Source-synchronous double data rate. Each data group (typically a byte) has its own strobe, DQS. DQS is edge-aligned with the data on reads, and the controller delays it by about a quarter clock period to sample mid-eye; on writes the controller sends DQS centre-aligned. |
SPI | The master drives the clock alongside its outgoing data, which makes the master-to-slave direction source-synchronous. Data from the slave does not get its own strobe: it pays the clock's round trip, which limits SPI's speed. |
DDR's split, edge-aligned one way and centre-aligned the other, puts the precise delay circuit in the controller for both directions. The memory devices, made in huge numbers, stay simple.
A board revision reroutes one byte lane's strobe around a connector, making it 8 mm longer than its data wires (illustrative). At 6.7 ps/mm that is about 54 ps of extra strobe delay. The receiver's quarter-period shift was calibrated for matched routing, so that lane's capture edge now sits 54 ps late, eating into the data's valid window. The lane works on most boards and fails on slow corners and at temperature.
Symptom: errors in one byte lane only, temperature-dependent.
Evidence: an eye diagram for that lane shows the capture point off-centre.
Fix: match the routing, or let the controller train a per-lane delay at start-up (lesson 11.4). Real memory controllers do the latter, because routing is never perfect.
dqs itself?Because the data changes at exactly those edges (edge-aligned). Capturing there would sample data in transition. The quarter-period shift moves each capture edge to the middle of a bit.
Two bits per strobe cycle, one per edge, so the strobe runs at 1 GHz.
Very little: data and strobe slow down together, so their relative timing is unchanged. Only mismatch between them matters. A common-clock link would lose 20% of its flight-time budget.
Source-synchronous links send a clock or strobe with the data, so the wire delay drops out of the budget and only the mismatch remains.
Edge-aligned strobes must be shifted a quarter period at the receiver; centre-aligned strobes can be used directly.
Double data rate puts a bit on each strobe edge; DDR memory gives each data group its own strobe.