Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
One period must cover clock-to-output, flight time, setup, skew and margin; at 500 ps the fixed terms alone may exceed it before trace length is added, and reads pay a round trip. Fast board links send timing with the data instead.
The last sample is 9.5 bits after the start edge, so drift must stay under about half a bit minus one oversampling tick: roughly (0.5 − 1/16)/9.5 ≈ 4.6% total with 16x oversampling, less in practice, shared between both ends.
To keep the memory simple: on reads it launches data and strobe together and the controller shifts DQS a quarter period; on writes the controller sends DQS centred so the memory samples directly.
The CDR recovers the clock from transitions and drifts by the ppm offset between them; with no transitions for long enough it samples the wrong bit. Protocols guarantee transitions with codes, stuffing or scrambling plus headers.
An alignment marker (an ordered set) is sent on all lanes at once; each lane buffers from its marker and all are read together once every lane has seen it. Buffers must cover the specified maximum skew at the highest rate.
Up to 600 ppm apart: once every 1/0.0006 ≈ 1,667 cycles, about every 16.7 µs at 100 MHz.
Clock compensation: the receiver's elastic buffer deletes or repeats SKP symbols to absorb the ppm difference between the recovered and local clocks; SKP carries no data.
Rarely: it removes clock trees and crossings but costs handshake round trips, wires or verified delay margins, and specialised tools. Most chips use GALS instead.
Task. A chip-to-chip link must carry 10 Gb/s over 30 cm of cable between two boards with separate 100 MHz oscillators of ±100 ppm. Choose a clocking scheme and list everything the protocol must provide to make it work. Then draw the receive path's clock domains.
A common clock or a strobe cannot close at 10 Gb/s over 30 cm, so use an embedded clock with CDR on one or more lanes. The protocol must: (1) guarantee transitions (8b/10b, or a sync-header block code with scrambling); (2) send filler symbols often enough for clock compensation: up to 200 ppm apart means one slip every 5,000 symbols, so filler well inside that; (3) if several lanes, send alignment markers on all lanes at once for deskew; (4) define start-up so the CDR locks before data (Part 11). Receive path: recovered clock, then an elastic buffer, then the link clock, then an async FIFO to the application clock.
Clock-to-output, flight time, setup, clock skew, margin (plus a hold check).
To sample the start bit in its middle (rejecting glitches) and to place every later sample near the middle of its bit.
The mismatch between strobe and data paths, and the accuracy of the strobe shift, not the flight time.
0.5 / 0.00025 = 2,000 bits.
A data block; both 01 and 10 contain a transition, so every block delivers an edge.
A bit is 125 ps, so 8 bits.
Mesochronous.
It only delays overflow; only removing or adding symbols can absorb a rate difference.
The request signal is delayed enough to arrive after the slowest data bit, at every corner.
Level: a two-flop synchroniser. Pulse: a pulse (toggle) synchroniser, with events spaced far enough apart.