An architect proposes connecting the blocks of a large chip with a network that has no clock at all. Every link would carry its own timing in its handshake, so there would be no clock tree to balance across the die and no clock-domain crossings between blocks running at different speeds. The room is interested, then sceptical: if clockless communication solves every problem in this part, why is almost nothing built that way?
How can data carry its own "valid" signal without any clock, and what does it cost?
The obvious clockless design adds one wire, "data is ready", next to the data, and the receiver captures when it rises. That is a strobe with no clock behind it. It breaks on the same issue as any strobe (lesson 1.3): the "ready" wire and the data wires do not arrive at exactly the same time, so the receiver can capture before the slowest data bit has settled. With no clock period to absorb the difference, the design needs either a guaranteed delay margin or a way to know, from the data itself, that it is complete.
Self-timed (asynchronous) circuits use one of two families, both built on the request/acknowledge handshakes of Part 3:
Family | How "valid" is signalled | Trade-off |
|---|---|---|
Bundled data | Ordinary binary data plus a request wire that is deliberately delayed so it always arrives after the slowest data bit; the receiver answers with an acknowledge | Cheap (one extra wire per bundle) but relies on a timing assumption: the request delay must exceed the data delay in every condition |
Delay-insensitive codes (for example dual-rail) | Each bit uses two wires: 01 means 0, 10 means 1, 00 means "not yet". The receiver knows a word is complete when every bit has left 00 (completion detection) | Correct whatever the wire delays, but twice the wires and extra logic to detect completion |
Either way, each transfer is a handshake with no clock: the sender says "here it is", the receiver says "got it", and the next transfer may start. The usual form is the four-phase protocol: request up, acknowledge up, request down, acknowledge down. The data must stay stable from request up until acknowledge up.
Compare a clocked and a self-timed link carrying one word (illustrative reasoning, no specific numbers needed):
Clocked (common clock) | Self-timed (four-phase, bundled) | |
|---|---|---|
Speed is set by | The worst-case path, every cycle | The actual delay of this transfer and the handshake round trips |
Clock distribution | A balanced tree across both ends | None |
Crossing between differently clocked blocks | Synchronisers or async FIFOs | None needed; but where a self-timed island meets clocked logic, a crossing is needed after all |
Per-word overhead | None beyond the clock | Two round trips of request and acknowledge (four-phase) |
Design tools and verification | Mature: static timing, standard flows | Specialised; timing assumptions (bundled data) must be verified separately |
The handshake round trips are why self-timed links are not automatically fast: over a long wire, waiting for an acknowledge before the next word costs as much as the flight time twice. Two-phase signalling (every transition counts) halves that, at the cost of more complex logic (lesson 3.5).
Approach | What it costs | When it wins |
|---|---|---|
Fully synchronous | Clock tree power and skew management | Most digital logic: tools, IP and verification all assume it |
Globally asynchronous, locally synchronous (GALS) | Crossings between islands | Large chips with many clock domains; islands stay ordinary synchronous logic |
Self-timed links between synchronous islands | Specialised design and verification of the links | Long on-chip interconnect where distributing one clock is hard |
Fully self-timed logic | Area (dual-rail), tools, verification effort | Niche: very low power, variable supply voltage, or extreme robustness to delay variation |
Where | What is used |
|---|---|
Crossings between clock domains | Four-phase and two-phase request/acknowledge handshakes, each signal through a synchroniser: the same handshake, made safe for clocked logic on both sides (the CDC course covers them in depth). |
Large SoCs | Usually GALS: synchronous islands joined by asynchronous FIFOs or synchronised handshakes, rather than self-timed logic. |
Research and specialised chips | Self-timed networks-on-chip and fully asynchronous processors have been built, typically where power or delay variation matters more than standard tooling. |
A team builds a bundled-data link and sizes the request delay from typical-corner timing (illustrative). At a slow process corner and low voltage, one data bit's path slows down more than the delay element does, and the receiver occasionally captures a word before that bit has settled. Nothing in the protocol detects it: bundled data is only correct while its timing assumption holds.
Symptom: rare single-bit errors at low voltage or high temperature.
Root cause: the request delay and the data paths did not track each other across corners.
Fix: verify the bundling constraint at every corner like any timing path, add margin, or switch the link to a delay-insensitive code where the cost is acceptable.
So it arrives after the slowest data bit has settled. With no clock period, that delay is the only thing guaranteeing the receiver captures complete data.
"Empty": no value yet. It lets the receiver tell an incomplete word from a complete one, and the return to 00 between words separates consecutive values.
Each word needs request up, acknowledge up, request down and acknowledge down, two full round trips across the wire, before the next word can start.
Self-timed links signal validity with the handshake itself: bundled data uses a delayed request; delay-insensitive codes make completion visible in the data.
They remove clock trees and crossings but pay in handshake round trips, wires, and verification of timing assumptions.
Most chips use GALS instead; the clockless handshake idea lives on in valid/ready, request/acknowledge and credits.