Every protocol in this table had to decide how its receiver knows when to sample. Read across a row for one protocol's whole answer; read down a column to see the range of answers to one sub-question.
Protocol | Clocking scheme | How the receiver finds each bit | How clock differences are handled |
|---|---|---|---|
APB, AXI (on chip) | Common clock | Samples on the shared clock edge | Not needed inside one domain; explicit crossings between domains |
SPI | Master-driven clock with the data | Samples on the clock edge set by its mode (CPOL, CPHA) | None needed: there is only the master's clock; slave-to-master data pays a round trip |
I2C | Master-driven clock line (SCL) | Data is sampled while SCL is high; SDA changes only while SCL is low | None needed; a slave may stretch SCL to slow the master |
UART | No clock: asynchronous framing | Re-locks on each start bit, samples mid-bit (commonly 16x oversampling) | Tolerates a few percent total mismatch per frame |
CAN | No clock: asynchronous with resynchronisation | Edges at least every six bits, guaranteed by bit stuffing | Receivers realign on edges throughout the frame |
DDR memory | Source-synchronous, double data rate | Each data group has its own strobe (DQS); edge-aligned on reads, centre-aligned on writes | Strobe and data share the delay; the controller trains capture timing |
PCI Express Gen1–2 | Embedded clock (CDR) | 8b/10b: at most five identical bits in a row | Elastic buffer adds or removes SKP symbols; lanes deskewed using ordered sets |
PCI Express Gen3–5 | Embedded clock (CDR) | 128b/130b: sync header with a transition on every block, scrambled data | Same: SKP-based clock compensation, lane deskew |
USB 2.0 | Embedded clock | NRZI plus a stuffed 0 after six 1s | Receiver tracks the transmitter's timing from transitions |
10 Gb/s Ethernet (10GBASE-R) | Embedded clock (CDR) | 64b/66b: sync header 01 or 10 on every block, scrambled payload | Receiver recovers and tracks the transmitter's clock |
Distance and rate pick the scheme. On chip and short: a common clock. Short, wide and fast: a strobe per group. Long or very fast: an embedded clock with CDR. Slow and cheap: no clock at all.
Embedded clocks hand work to the protocol. Every CDR protocol in the table guarantees transitions (a code, stuffing or a sync header) and, for continuous streams, defines filler symbols for clock compensation.
Master-driven clocks are simple but one-directional. SPI and I2C avoid clock-difference problems by having only one clock, and pay for it in speed on the return path.