Each row is one protocol; each column one question. Read down a column to see the range of answers to one question, and across a row to see how one protocol's answers fit its constraints. Details and sources are on each protocol's page.
Protocol | When is data valid? | Is the receiver ready? | How much may I send? |
|---|---|---|---|
No clock; start bit re-aligns | No | Nothing in the frame (RTS/CTS optional) | |
Master's clock | No | Master paces everything | |
Master's clock, stable while SCL high | ACK per byte; clock stretching | Per byte | |
Common clock | PREADY wait states | One transfer | |
Common clock | HREADY wait states | One in the data phase | |
Common clock | VALID/READY per channel | READY back-pressure | |
Common clock | TVALID/TREADY | TREADY back-pressure | |
Embedded clock, CDR | Credits | Six credit types | |
Strobes (DQS) | No: fixed latency | Controller owns timing | |
On-chip clocks | Link credits | Link and protocol credits | |
Embedded clock | No per-frame handshake | Lossy; PAUSE/PFC optional | |
Recovered from transitions | ACK/NAK/STALL to host tokens | NAK | |
Forwarded clock | Inherited credits | Inherited credits | |
Embedded clock (PCIe PHY) | Credits | Per protocol and class |
Protocol | How many in flight? | In what order? | What if bits go wrong? | Start-up |
|---|---|---|---|---|
One character | As sent | Parity, framing error | Pre-configured | |
One transaction | As shifted | Nothing | Pre-configured | |
One transaction | Strict | Missing ACK only | Fixed addresses | |
One | Strict | PSLVERR | Fixed map | |
Pipeline of two | Strict | ERROR response | Fixed map | |
Many, by ID | Per ID | SLVERR/DECERR, no retry | Reset rules | |
One beat per cycle | Per stream | Not addressed | Reset rules | |
Many, by tag | Ordering table | LCRC + replay, ECRC, FEC (Gen6) | LTSSM, enumeration | |
Many banks | Controller reorders, same-address order kept | ECC DIMMs | Training | |
Many, by TxnID | Home node per address | Error responses, poison | LinkActive | |
Many frames | Per link; end to end above | CRC-32 then drop; FEC | Auto-negotiation | |
One per bus (USB 2.0) | Per endpoint | CRC + retry, DATA0/1 | Enumeration | |
Inherited | Inherited | CRC + retry in adapter | Training + negotiation | |
Many, per protocol | .io as PCIe; own rules for .cache/.mem | CRC + retry | Negotiated in PCIe training |
Distance decides clocking: shared clocks on chip, strobes on boards, embedded clocks over connectors and cables, forwarded clocks again inside packages.
Handshakes become credits as soon as round trips grow or links get long.
Concurrency arrives with latency: protocols facing DRAM or long links add IDs, tags and ordering rules.
Reliability follows the error rate: nothing on chip, detection on simple serial buses, replay and FEC on fast links.
Interoperability brings bring-up: negotiation, enumeration and compliance appear wherever unknown partners meet.