assert property (@(posedge clk) disable iff (!rst_n) valid && !ready |=> $stable(data)); with a companion valid && !ready |=> valid and a cover for long stalls. Likely follow-up: Why |=> rather than |->?

Add a skid buffer: when ready falls, the word already sent is caught in a spare register and replayed, so full throughput survives a registered ready. Likely follow-up: How many entries does it need, and why?

At least 20 flits; fewer limits throughput to buffer/round-trip, e.g. 8 flits gives 40%. Likely follow-up: What extra latency counts in the round trip?

So one class (requests) cannot use every credit and block another (completions) that it depends on: message-dependent deadlock. Likely follow-up: What is the minimum reservation per class?

The sender's count disagrees with the receiver's empty buffer: overflow, or permanently reduced throughput. Likely follow-up: How does PCIe avoid it?

When the hop's round trip is several cycles (long wires, many register slices), so ready would need deep skid buffers. Likely follow-up: What does credit initialisation require at start-up?

A blocked packet at a queue head stalls packets behind it bound elsewhere; virtual output queues or virtual channels remove it. Likely follow-up: What throughput does a FIFO input-queued switch saturate at?

If the receiver waits to return credits until a batch is full and the sender has fewer credits than the batch, no batch ever forms. Likely follow-up: How would you fix it while keeping batching?

Little's law: 0.5e9 lines/s × 200 ns = 100 outstanding. Likely follow-up: What happens to throughput if latency doubles?

Keep same-ID transactions from one manager on one path, or block a same-ID request to a different target until earlier ones complete; remap IDs uniquely. Likely follow-up: What breaks if two managers' IDs collide after remapping?

One queue of predictions per ordering domain (ID or tag), compare each response with the oldest in its queue, report unexpected and missing responses. Likely follow-up: What does a duplicate response do to that queue?

Not guaranteed; there is no read/write ordering. Wait for the write response before issuing the read. Likely follow-up: Does the same ID help?

A requester that took the early response as proof of completion may signal a consumer before the data is visible. Likely follow-up: Where in a system is early acknowledgement safe?

Producer-consumer: the read may be the consumer's check of data written earlier; passing it could return stale data. Likely follow-up: Why are posted writes allowed to pass reads?

Area for every outstanding response and latency for responses waiting on earlier ones; sized by outstanding count. Likely follow-up: When is out-of-order completion without a reorder buffer acceptable?

Several completions for one read, in address order for that read, interleaved with others' completions, matched by tag and byte count. Likely follow-up: What field tells it a read is complete?

Make the interrupt a posted write behind the data in the same ordered stream (PCIe MSI), or read back before signalling. Likely follow-up: What if the interrupt is a sideband wire?

The place where requests to an address are ordered, such as a home node or a memory controller queue; ordering guarantees are only as strong as what happens before it. Likely follow-up: Why can two paths to one target break ordering?

A low-priority holder blocks a high-priority waiter while medium-priority traffic runs; fix with priority inheritance or bounded holding. Likely follow-up: Give a real example.

A ring's channel dependency graph is a cycle; add a dateline with two virtual channels so the graph is acyclic. Likely follow-up: What breaks if adaptive routing is added?

That every endpoint eventually consumes messages it receives regardless of what it is waiting for; violating it creates message-dependent deadlock. Likely follow-up: How does PCIe guarantee completions are consumed?

Retry avoids worst-case buffers but risks livelock; protocol credits (CHI) make retry fair and bounded. Likely follow-up: How does a protocol credit prevent livelock?

Find the stuck handshake, the missing enabling condition, the state behind it, check it with a conservation rule, go back to the first wrong cycle. Likely follow-up: What conservation rule applies to a credit link?

Deadlock is a liveness failure; simulation only explores generated sequences. Use a dependency argument or formal. Likely follow-up: How would you bound it to catch it in simulation?

Capture state on expiry (outstanding transactions, FSM states, a frozen trace), report which requester was stuck, then recover. Likely follow-up: What should the timeout value be?

Requests keep being retried and rejected in a pattern where none progresses; break it with randomised back-off, fairness or reservations. Likely follow-up: How do protocol credits avoid it?

Window ≤ 2^n − 1, so n = 6 (63). Likely follow-up: And for selective repeat?

It must hold every unacknowledged packet: link rate × ACK round trip (including ACK coalescing and processing), in packets or bytes. Likely follow-up: What happens if ACKs are coalesced too much?

LCRC protects each link and is regenerated at each hop; ECRC is end to end, covering data inside switches. Likely follow-up: When is ECRC worth enabling?

The transaction completes; only the consumer of the data gets an error, so nothing hangs and the error is contained. Likely follow-up: What if a bridge strips the poison bit?

PAM4 raised the raw error rate so replay alone would cost too much bandwidth; FEC corrects most errors in place, with CRC and replay behind it. Likely follow-up: Why fixed-size flits?

16e9 × 1e-12 = 0.016 per second, about 1,400 per day. Likely follow-up: What undetected rate does a 32-bit CRC give across a fleet?

They must complete with errors (or time out), credits and replay state are discarded, and traffic resumes only after retraining and re-initialisation. Likely follow-up: What is different about link recovery?

Each advertises its abilities, both take the highest common setting by the same rule, confirm it, and fall back if it fails to train. Likely follow-up: Why confirm the advertisement?

Senders set them to 0; receivers ignore them, so later versions can give them meaning. Likely follow-up: What if receivers checked them?

Blocks leave reset at different times; explicit readiness (credits, link-up) means whichever starts first simply waits. Likely follow-up: Name a block that commonly leaves reset late.

(150 − 10) × 10 / (100 − 10) ≈ 15.6 µs. Likely follow-up: How would you choose the idle timeout?

Only it knows about outstanding or imminent work; denial prevents being cut off mid-transaction. Likely follow-up: What must it do before accepting?

The knowledge that the copy is the only one, so the first write needs no bus transaction. Likely follow-up: What does O add?

When broadcast traffic and lookups to every cache dominate; directories message only holders at the cost of indirection. Likely follow-up: What is back-invalidation?

No; coherence orders one location, the memory model orders across locations, enforced by barriers. Likely follow-up: Give the flag-and-data example.

I/O coherent interconnect, or clean before device reads and invalidate around device writes with barriers and line-aligned buffers. Likely follow-up: Why invalidate after the DMA too?

At or in front of the target, using unforgeable attributes carried with each request; untrusted requesters get attributes from the fabric. Likely follow-up: What should a bridge without a security bit drive?

So DMA can only reach memory software mapped for that device, keyed on an identity it cannot forge. Likely follow-up: What does ATS require on unmap?

Protocol coverage: handshake timing per channel, every outstanding count to the maximum, burst types, lengths, sizes and 4 KB edges, ordering cases, all responses, reset in flight, key crosses, every assertion's trigger. Likely follow-up: Why isn't code coverage enough?

For handshakes, counters, credit loops, FIFOs, arbiters, ordering and deadlock; assume the partner's rules, assert your own, cover against over-constraint. Likely follow-up: What does a bounded proof tell you?

Independence from your own reading of the specification, plus an agent, checker, coverage and compliance tests already exercised widely. Likely follow-up: How do you get independence for an in-house protocol?

Status and sticky first-error capture, counters, timestamped trace frozen by triggers, and a debug path that works when the fabric is hung. Likely follow-up: What should trigger the freeze?

Liveness; bound it, check for leftovers after draining, or prove it formally. Likely follow-up: How would you pick the bound?

It samples only transfer cycles and closes the transaction on the protocol's end marker or final beat. Likely follow-up: What if it samples on valid alone?