"Design the interconnect for a camera SoC." Forty-five minutes, a whiteboard, no other information. The interviewer wants to see how you turn a vague request into requirements, numbers, a structure and justified choices, and how you respond when they change a requirement halfway through.
How do you walk through an open interconnect design question end to end?
Step | Do | Time |
|---|---|---|
1. Clarify | Agents, traffic types, bandwidth and latency targets, power, area, safety, security, who builds what | 5 min |
2. Size | Bandwidth per flow, total, outstanding by Little's law, buffer sizes from round trips | 10 min |
3. Structure | Topology: where traffic meets, what is shared, where crossings and bridges are | 10 min |
4. Choose per question | Handshake, flow control, ordering, arbitration and QoS, deadlock, errors, power, coherence, security | 10 min |
5. Verify and observe | Assertions, models, coverage, formal targets, silicon debug | 5 min |
6. Adapt | Respond to a changed requirement by naming which choices it affects | 5 min |
Clarified: an image sensor delivering 4K video at 60 frames per second into DRAM, an image processor reading and writing frames, a video encoder, a CPU cluster and a display. Real-time deadlines for sensor and display.
Sensor write: 3840 x 2160 pixels x 2 bytes x 60 /s = about 1.0 GB/s
Processor: reads 1.0 + writes 1.0 = about 2.0 GB/s
Encoder: reads about 1.0 GB/s, writes little
Display: 3840 x 2160 x 4 bytes x 60 /s = about 2.0 GB/s
Total to DRAM: about 6 GB/s plus CPU trafficStructure: AXI4 to a memory controller; streaming engines on AXI-Stream between processing stages to avoid DRAM round trips where possible.
QoS: sensor and display are real-time (buffers would underflow or overflow); give them high priority with bandwidth regulation so they cannot starve the CPU; the encoder is best effort.
Buffering: sensor and display FIFOs sized to cover the worst-case DRAM latency under load at their rates.
Ordering: per-ID ordering is enough; frames are independent.
Power: idle engines quiesced and clock-gated with request/accept/deny handshakes.
Verify: bandwidth and latency model before RTL; assertions per interface; underflow monitors on display.
Clarified: a 100 Gb/s network card on PCI Express, many queues, low latency for small packets.
Line rate: 100 Gb/s = 12.5 GB/s each way
Minimum packets: 84 bytes on the wire -> about 149 million packets/s
Descriptor reads: one per packet (or batched)
Outstanding DMA reads: 12.5 GB/s x 1 µs host latency = 12.5 KB in flight
-> about 49 reads of 256 bytes outstandingStructure: descriptor rings in host memory with doorbells (lesson 5.16); DMA engines; interrupt moderation.
Transactions: posted writes for receive data and completions (they are fast and ordered behind data); reads for transmit data and descriptors, with enough tags.
Ordering: an interrupt (MSI) must follow its data: both are posted writes in one ordered stream (fact P26).
Isolation: SR-IOV virtual functions per virtual machine, IOMMU translation, per-queue rate limits.
Reliability: PCIe replay handles links; end-to-end checksums for packets.
Verify: per-queue scoreboards, ordering checks for interrupts after data, error injection.
Clarified: 16 cores with private caches, a shared last-level cache, coherent accelerators, DRAM.
Coherence: invalidation-based, MOESI-like states; a directory or snoop filter at the shared cache's home slices, so snoops go only to holders.
Interconnect: a message-based protocol (CHI-like) on a mesh; separate request, response, snoop and data channels with link credits.
Deadlock: message classes on separate virtual channels; homes retry with protocol credits instead of worst-case buffers.
Sizing: outstanding misses per core by Little's law against DRAM and remote latency; snoop filter sized for the total private cache capacity with margin.
Accelerators: fully coherent if they reuse data, I/O coherent otherwise.
Verify: formal on the coherence tables and race cases; litmus tests for the memory model; directed races between writebacks and forwards.
Change | Name what it affects |
|---|---|
"Now the display must never underflow, even at maximum CPU load" | QoS guarantees, regulator settings, FIFO depth, DRAM scheduling priority |
"Latency must halve" | Outstanding limits (Little's law changes), buffering, hop count, whether to cut through |
"It must meet ASIL B" | Interface protection, ECC, timeouts, fault reporting and coverage metrics (lesson 10.17) |
"Two tenants will share it" | Isolation: IOMMU, per-tenant queues and regulators, partitioning (lesson 14.6) |
The numbers decide the mechanisms: outstanding counts set tags and buffers, round trips decide ready or credits, error rates decide replay or FEC.
So it cannot overtake the DMA writes it announces; posted writes from one function stay in order, so software sees the data when the interrupt arrives.
Clarify, size, structure, choose per question, verify, adapt.
Numbers first: bandwidth per flow, Little's law, round trips, error rates.
When requirements change, name precisely which choices they affect.