A contract between two independently designed blocks: promises about what values mean, when they count, what sequences are allowed, and what happens in reset and on errors, each checkable on the wires. It deliberately leaves internal choices such as latency and buffering open.

Both, on different interfaces: a target on its register port, an initiator on its data port (consumer on reads, producer on writes), and the producer of an interrupt. Roles belong to interfaces, not blocks.

The specification's: it left the timing layer in prose or unstated. The fix is a numbered rule, such as "data is valid in every cycle in which valid is high", plus a timing diagram as an example.

One setup cycle (PSEL high, PENABLE low, address and data valid), then access cycles with PENABLE high; PREADY low for one cycle, then high. The write completes at the rising edge where PSEL, PENABLE and PREADY are all sampled high, and address and data stay constant until then.

Model the pair as one product machine including the wires, enumerate every reachable state by trying every move of each side in any order, and check that no reachable state other than the intended end has no possible move. For real RTL, express it as an assertion and use a formal tool.

Skew between parallel wires is roughly fixed in picoseconds while bit times shrink, so the common sampling window vanishes. Serial lanes avoid inter-wire skew and save pins and power; the receiver takes on clock recovery and framing.

Each link's CRC protects only that wire; a switch recomputes it, so corruption inside a switch passes both checks. The end-to-end argument says correctness of delivery needs an end-to-end check; the per-hop CRC with replay is a performance mechanism that fixes wire errors locally.

When data flows one way, in order, from one producer to one consumer, exactly once. Use memory-mapped for shared, revisited or software-visible data, and then specify notification and ordering.

1. A reading moves on a rising edge where valid and ready are both high (count such edges). 2. data is meaningful only while valid is high (nothing to check otherwise). 3. Once valid is high, valid and data stay unchanged until the reading moves (if valid and not ready at an edge, the next cycle has the same valid and data). 4. valid does not wait for ready (design review or formal proof). 5. During reset the sender drives valid low (valid is 0 in every reset cycle). 6. The controller raises ready within a stated bound, for example 100 cycles of valid (a bounded check in simulation). Left open on purpose: how the sensor produces readings and how the controller stores them.

Exceptional cases, especially reset and errors.

The target (the memory). The initiator of a read is the consumer.

Signals, meaning and timing (including sequencing rules).

The values just after a rising edge, which are the values sampled at the next edge.

The requester returns to idle only after seeing ack low.

Addressing and arbitration, including what happens when two agents drive at once.

A quarter bit = 25 ps means a 100 ps bit time: 10 Gb/s.

The link layer: the function concerns one hop, whose two ends are the only parties with the knowledge it needs.

A write to memory is silent; the consumer cannot tell it happened without a flag, interrupt or message, and the protocol must order that notification after the data.

No. Protocol rules must hold for every timing of the other side; a rule that depends on one timing breaks when that side moves to another clock or gets busier.