This page puts the ideas of Part 0 side by side for ten real protocols. Read a row to see one protocol's basic shape; read a column to see how differently the same question can be answered. Every entry is stated the way the course's fact sheet states it.
Protocol | Topology | Duplex | Roles | Layers | Model |
|---|---|---|---|---|---|
UART | Point-to-point | Full duplex, one line per direction | Symmetric: either side may send | One (framing on the line) | Stream of characters |
SPI | One master, slaves picked by chip select | Full duplex | Master drives the clock and starts every transfer | One | Stream of bits per transfer |
I2C | Shared bus, open-drain | Half duplex on SDA | Masters start transfers and arbitrate; slaves answer | One | Addressed transfers (memory-like registers) |
APB | Point-to-point interface into a fabric | Separate read and write data | Requester and completer | One | Memory (register reads and writes) |
AXI | Point-to-point interfaces joined by interconnects | Separate channels per direction | Master and slave per interface | One | Memory |
AXI-Stream | Point-to-point | One way (data), plus TREADY back | Producer and consumer | One | Stream, with TLAST boundaries |
PCI Express | Point-to-point links joined by switches | Dual simplex lanes | Requester and completer, both on one link | Three: transaction, data link, physical | Mainly memory, plus messages |
Ethernet | Point-to-point links joined by switches (classic shared media in the past) | Full duplex on modern links | Symmetric stations | Physical and data link; upper layers (IP, TCP) above | Messages (frames) |
DDR memory | Controller to memory devices | Half duplex data bus (reads and writes take turns) | Controller initiates everything | Controller and PHY | Memory |
CAN | Shared bus | Half duplex | Any node may send; bitwise arbitration | One | Messages identified by ID |
Shared buses take turns and need arbitration (I2C, CAN, and the DDR data bus between reads and writes). Point-to-point links do not, which is one reason fast protocols are point-to-point and use switches for fan-out.
Roles split cleanly on chip (AXI, APB: one master side, one slave side per interface) and mix on links (PCI Express: the same device is a requester and a completer over one link). Mixing roles is cheaper in pins and harder to keep deadlock-free.
Only the long-distance protocols are layered (PCI Express, Ethernet). On chip, wires are short and reliable enough that one layer suffices; off chip, a link layer earns its keep with CRC, replay and credits.
The communication model follows the traffic: memory where data is shared or revisited (AXI, APB, DDR), stream where it flows (AXI-Stream, UART), messages where self-contained units are exchanged (Ethernet, CAN).