A team needs to connect eight sensors to a controller. One engineer proposes a separate link to each sensor; another proposes one shared pair of wires that all eight hang on. Both work. The first needs eight times the pins; the second needs addresses, a rule for who may talk, and a way to recover when two talk at once. The choice was made before anyone had written a single signal name, and it decided most of the protocol.
What are the basic shapes a channel can take, and what does each force the protocol to solve?
It is tempting to treat wiring as a physical detail to settle late: design the protocol, then route the wires. But the shape of the channel decides whether you need addresses, arbitration and collision handling at all, whether both sides can talk at once, and how fast you can go. Choose the protocol first and the wiring second, and you often find the protocol has rules the wiring cannot support, or the wiring has capacity the protocol cannot use.
Every channel is described by three choices, each made separately:
Choice | Options | What it forces on the protocol |
|---|---|---|
Topology: who is wired to whom | Point-to-point; shared bus; switched | Shared: addresses, arbitration, collisions. Switched: routing, buffering in the switch. Point-to-point: none of these |
Duplex: who may talk when | Simplex (one way only); half duplex (both ways, taking turns); full duplex (both ways at once) | Half duplex: a turnaround rule. Simplex: a separate channel for anything coming back |
Width: how many data wires | Parallel (many wires, one bit each per clock); serial (one or a few wires, many bits in sequence) | Parallel: skew between wires. Serial: framing and clock recovery (Parts 1 and 2) |
A parallel bus sends all bits of a word at once, which sounds faster. The problem is skew: the wires are never exactly the same length or load, so bits launched together arrive at slightly different times, and the receiver must sample all of them in a window where every one is stable. Skew is roughly fixed in picoseconds, while the bit time shrinks as the rate goes up. With illustrative numbers:
Skew between wires on a board: about 100 ps (illustrative)
At 100 Mb/s per wire: bit time = 10,000 ps -> skew uses 1% of each bit
At 1 Gb/s per wire: bit time = 1,000 ps -> skew uses 10% of each bit
At 10 Gb/s per wire: bit time = 100 ps -> skew uses 100% of each bit: no sampling window leftA serial link has no skew between data wires, because there is only one (or each lane is aligned separately, lesson 1.5). It also needs fewer pins and less power per bit at high rates. The price is that the receiver must find the bits and the word boundaries itself, which is what Parts 1 and 2 are about. Differential signalling, two wires carrying opposite copies of the signal, is the usual companion: the receiver looks at the difference, so noise that hits both wires equally cancels, which lets the swing be small and the rate high.
Option | What it costs | When it wins |
|---|---|---|
Point-to-point | One link (and pins) per pair of agents | Few agents, high bandwidth, simple protocol |
Shared bus | Addresses, arbitration, one transfer at a time; electrical loading limits speed | Many low-rate agents, few pins (sensors, configuration) |
Switched | A switch with buffers and routing; extra latency per hop | Many high-rate agents (networks, large SoC fabrics) |
Half duplex | Turnaround time between directions; a rule for who talks | Pin-limited links where traffic is mostly one way at a time |
Full duplex | Twice the wires (or more complex electronics) | Traffic in both directions at once, such as requests one way and responses the other |
Parallel | Skew limits rate; many pins | Short distances, moderate rates (on-chip buses, memory interfaces with strobes) |
Serial | Clock recovery, framing, encoding overhead | Long distances or very high rates (chip-to-chip, box-to-box) |
Protocol | Topology | Duplex | Width |
|---|---|---|---|
I2C | Shared bus (open-drain, wired-AND) | Half duplex on one data line (SDA) | Serial, with a clock line (SCL) |
SPI | One master to slaves, each selected by its own chip select | Full duplex: data travels both ways on every clock | Serial, master-driven clock |
UART | Point-to-point | Full duplex with one line per direction | Serial, no clock |
AXI / APB | Point-to-point interfaces, joined into fabrics by interconnects | Separate channels for each direction | Parallel, on chip |
PCI Express | Point-to-point links joined by switches | Dual simplex: each lane has one differential pair in each direction | Serial, 1 to 32 lanes per link |
Notice the pattern: the slow, pin-starved protocols share wires and take turns; the fast ones are point-to-point, full duplex and serial, and get to many agents with switches.
A team extends a shared configuration bus from four devices to twelve to save pins (illustrative). Functionally nothing changes. But the bus wire now has three times the load, its edges slow down, and at the old clock rate some devices sample data before it has settled. The result is intermittent misreads on the devices farthest along the wire. The fix was to halve the bus clock, which was acceptable for configuration traffic, and the general lesson is that a shared bus trades pins for speed: every device you add makes it slower.
On every clock the master shifts one bit out on its data-out line and one bit in on its data-in line, so both directions move at once. It costs a second data wire compared with a half-duplex scheme.
Addressing (which agent a transfer is for) and a rule for who may drive the bus, including what happens when two try at once.
Half a bit = 50 ps means a bit time of 100 ps, which is 10 Gb/s per wire.
Topology (point-to-point, shared, switched), duplex (simplex, half, full) and width (parallel, serial) are three separate choices made before any signal is named.
Sharing wires forces addressing and arbitration; switching forces routing and buffering.
Fast links went serial because skew between parallel wires is fixed while bit times shrink; serial moves the burden to clock recovery and framing.