Top Clock Tree Architecture: Review Checklist

Review checklist

Review Checklist for Top Clock Tree Architecture focuses on clock skew budget, insertion delay, CTS closure rate. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

• Baseline manifest and revision are explicit.

• Boundary contracts for this topic are current and approved.

• Ownership map covers all open issues.

• Focused and full regression evidence both exist.

• Residual risks are either closed or bounded via waiver policy.

• Owners signed: clock architect, CTS owner, STA owner.

Signoff ownership

OWNERSHIP MAP — Top Clock Tree Architecture

artifact             owner
-----------------    -----------------
primary owner     clock architect
co-owner          CTS owner
review owner      STA owner

No top-level issue should remain ownerless beyond one review cycle.

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Clock architecture partitions domains, generated clocks, and distribution strategy so top-level timing remains tractable under MMMC and PVT spread.

Metric: clock skew budget, insertion delay, CTS closure rate