Hardware / software view

Reset defaults and register semantics must match boot code assumptions.

What firmware teams feel

• Boot instability

• Contract drift after minor RTL change

Contract impact

• Register defaults

• interrupt behavior

• clock/reset assumptions

Build and integration notes

• Synth/PD assumptions can invalidate software expectations

Mitigations

• Versioned contracts

• joint hw/sw readiness reviews

HW/SW CONTRACT — I/O Subsystem Integration
// firmware init order must match reset/clock release assumptions

Layer software touches

SOC INTEGRATION LAYERS — I/O Subsystem Integration

layer               owns                          failure mode
-----------------   ---------------------------   ------------------------
architecture        partition + contracts         impossible budgets
ip handoff          models + collateral           integration mismatch
fabric/clock/reset  global behavior               domain deadlock
physical/package    route + SI/PI + IO            late closure churn
signoff process     manifests + waivers           non-reproducible claims
program governance  owners + escalations          schedule collapse

SoC deep dive

Address, interrupt, and IO contracts are where hardware/software alignment is won or lost.

Concept diagram

HW/SW CONTRACT
address map + interrupt model + io defaults -> firmware behavior

Metric graph

BOOT REGRESSION SOURCES
map churn █████
reset defaults ████
driver mismatch ███

Reports and artifacts

• address decode audit

• interrupt latency report

• IO bring-up checklist

• boot contract review

Mini case study

A map alias issue caused sporadic peripheral misconfiguration despite clean block-level tests.

Debug branches

• Freeze address map baseline

• Audit reset defaults

• Validate firmware assumptions

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

I/O integration couples pinmux, clocks, resets, DMA, and register semantics; mismatched assumptions usually surface as bring-up instability.

Metric: I/O bring-up pass rate, register-map mismatch defects