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Course contents

  • How to Use This Course
  • SoC Integration Metrics Reference
  • SoC Integration Glossary
  • Reading Path
  • Hierarchy & Budget Contracts61
  • Clock & Reset Architecture61
  • Bus Fabrics & Interconnect61
  • Memory Maps & I/O61
  • IP Integration & Handoff61
  • Package & Interface61
    • Bump Map & Escape Planning
      • Bump Map & Escape Planning: Mechanism
      • Bump Map & Escape Planning: Inputs & Outputs
      • Bump Map & Escape Planning: Reports & Metrics
      • Bump Map & Escape Planning: Debug Playbook
      • Bump Map & Escape Planning: Worked Example
      • Bump Map & Escape Planning: Pitfalls & Red Flags
      • Bump Map & Escape Planning: Interview Drills
      • Bump Map & Escape Planning: Review Checklist
      • Bump Map & Escape Planning: Theory Deep Dive
      • Bump Map & Escape Planning: Design Space
      • Bump Map & Escape Planning: Expanded Case Study
      • Bump Map & Escape Planning: Step-by-Step Walkthrough
      • Bump Map & Escape Planning: Comparison Matrix
      • Bump Map & Escape Planning: Software / Programmer View
      • Bump Map & Escape Planning: Silicon PPA Impact
    • Package SI/PI Contracts
    • Chip-Package I/O Co-design
    • Package Bring-up & Failures
    • Package & Interface: Tricky Q&A
  • Chip-Level Signoff61
  • SoC Interview Prep4
  • SoC Integration Cheatsheet
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‹Bump Map & Escape Planning
  1. Topics
  2. SoC Design
  3. Package & Interface
  4. Bump Map & Escape Planning
  5. Bump Map & Escape Planning: Comparison Matrix

SoC Integration · All levels

Bump Map & Escape Planning: Comparison Matrix

Comparison Matrix for Bump Map & Escape Planning.

On this page

    Comparison matrix

    Bump and IO strategies trade SI/PI margin against routability.

    Diagram
    +------------------+----------------+----------------+----------------+
    | Approach         | Strength       | Weakness       | Best when      |
    +------------------+----------------+----------------+----------------+
    | Strict           | predictable    | slower early   | new program    |
    | Balanced         | practical      | needs rigor    | stable teams   |
    | Aggressive       | fast           | escape risk    | late schedule  |
    | Re-architect     | durable        | expensive      | recurring failures |
    +------------------+----------------+----------------+----------------+

    When to choose each approach

    • Pick the approach based on residual silicon risk, not only schedule pressure.

    Review traps

    • Policy-only arguments without artifact evidence

    • Unbounded waivers

    Evidence comparison

    Diagram
    INTEGRATION EVIDENCE MATRIX — Bump Map & Escape Planning
    
    +-------------------+------------------------+--------------------------+-------------------------+
    | Evidence           | Tells you              | Does not prove           | Next action             |
    +-------------------+------------------------+--------------------------+-------------------------+
    | Manifest diff      | baseline changed       | root cause itself        | isolate first delta     |
    | Domain trace       | where behavior diverged| ownership accountability | map to contract owner   |
    | Signoff dashboard  | closure posture        | reproducibility quality  | verify source artifacts |
    | Bring-up logs       | software-visible symptom| physical/timing cause   | correlate with HW trace |
    | Waiver register    | accepted residual risk | technical closure        | review expiry criteria  |
    +-------------------+------------------------+--------------------------+-------------------------+

    SoC deep dive

    Package assumptions must be treated as first-class chip constraints.

    Concept diagram

    Diagram
    PACKAGE CO-DESIGN
    die io <-> package routing <-> board constraints

    Metric graph

    Diagram
    PACKAGE RISK MIX
    SI margin █████
    power integrity ████
    lane mapping ███

    Reports and artifacts

    • bump map revision log

    • SI/PI margin report

    • IO co-design checklist

    • package bring-up failures

    Mini case study

    Link degradation on product board came from package routing assumptions not reflected in pre-silicon model.

    Debug branches

    • Compare package model versions

    • Audit lane mapping

    • Correlate SI/PI margins to failures

    Senior review question

    Ask: what baseline, owner, and artifact prove this topic is truly closed?

    Key takeaways

    • State baseline manifest and owner with every closure metric.

    • Run cross-domain regression after every top-level fix.

    Common pitfalls

    • Comparing results across different manifests.

    • Unowned issues slipping through review cycles.

    • Waiving risks without expiry and validation plan.

    Principal SoC review addendum

    Bump maps and escape strategy determine routability, IR quality, and package feasibility before final pad-ring freeze.

    Metric: bump congestion, reroute churn, escape DRC violations

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    See also

    • Bump Map & Escape Planning: Mechanism
    • Bump Map & Escape Planning: Inputs & Outputs
    • Bump Map & Escape Planning: Reports & Metrics