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Course contents

  • Start Here6
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive36
  • SystemVerilog Assertions — Interview-Critical Deep Dive40
  • Functional Coverage in SystemVerilog22
  • Testbench Architecture in SystemVerilog23
  • Advanced Language & Integration25
    • DPI-C: Calling C from SystemVerilog
    • bind: Attaching Verification to RTL
    • Macros, Defines & Compilation
      • `define & Text Macros
      • `ifdef & Conditional Compilation
      • `include & Guard Discipline
      • Debugging Macro Problems
    • Plusargs, Files & Runtime Configuration
    • Simulation Performance & TB Memory
    • RTL/TB Boundaries, Races & Timing
  • Senior & Interview Preparation21
  • Principal-Level Verification28
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‹Advanced Language & Integration
  1. Topics
  2. SystemVerilog
  3. Advanced Language & Integration
  4. Macros, Defines & Compilation

Part 7 · Advanced & Integration · Intermediate

Macros, Defines & Compilation

Text macros, conditional compilation, include guards, and macro debugging for reliable builds.

  • 4topics
  • 4lessons

The SystemVerilog preprocessor runs before the compiler sees the code. ` define`, ifdef` and include`` do pure text substitution with no type checking and no scope.

Diagram
TOPIC MAP — PREPROCESSOR TO SIMULATOR

  source.sv ──► PREPROCESSOR ──► expanded text ──► COMPILER ──► ...
                    │
       ┌────────────┼──────────────┐
       │            │              │
       ▼            ▼              ▼
   `define       `ifdef        `include
   text macros  conditional    file paste
   (lesson 1)   compilation    + guards
                (lesson 2)     (lesson 3)
       │            │              │
       └────────────┴──────────────┘
                    │
                    ▼
        Debugging macro problems (lesson 4:
        expansion errors, loud guards, safe
        log macros, build stages)

Lesson

Covers

Text macros

Object-like and function-like macros, the parens rule, multiline bodies, and macros versus parameters.

Conditional compilation

` ifdef`` selection, command-line defines, sim-versus-synthesis guards, and configuration discipline.

Include guards

Textual paste semantics, the double-include failure, the guard pattern, and search paths.

Debugging macros

Expansion-error reading, loud configuration guards, a safe log macro, and build stages.

Check yourself One build prints a banner macro and another stays silent, with identical source files. Name two preprocessor-level causes.

A missing command-line define (` ifdef`` on a misspelled or unset name is silently false), or a macro redefined later in compile order so the second build expands a different body.

Interview

Expect whiteboard fluency, not trivia.

  • Write a parenthesized function-like macro and explain each paren.

  • Explain ` ifdef` versus a run-time if, and include`` versus a package import.

  • Debug a dangling-else at a macro call site by re-expanding the macro by hand.

PreviousNext: `define & Text Macros

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Up next`define & Text Macros

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See also

  • DPI-C: Calling C from SystemVerilog
  • bind: Attaching Verification to RTL
  • Plusargs, Files & Runtime Configuration