The boundary between testbench and RTL decides which value a same-edge access sees. A driver can win or lose its race, a monitor can report the old or the new value, and an assertion can disagree with a display, all from the same code.
Symptom | Cause | Lesson |
|---|---|---|
Value off by exactly one cycle | Same-region drive or sample race | |
Same test, different result per tool | Simulator-chosen process order | |
Assertion disagrees with display | Different scheduling-region snapshots | |
Need to reach inside the DUT | Uncontrolled cross-boundary access |
Lesson | What changes |
|---|---|
A same-edge race walked cycle by cycle, with the off-by-one checklist. | |
Skewed sample and drive points that remove the race by construction. | |
The full region pipeline and where each kind of code runs. | |
Controlled rule-breaking: XMR discipline and audited force and release. |
Neither read is illegal, but the monitor's report is wrong for checking: it saw a different region of the time step than the DUT did. That is a TB/RTL race. Sample through a clocking block (Preponed) so the monitor sees what the flop captured.