RTL/TB Boundaries, Races & Timing

Overview

The boundary between testbench and RTL is where the most confusing bugs in verification live: a monitor that samples the old or new value depending on which simulator you run , a driver that wins or loses a same-edge race after an unrelated code change, an assertion that disagrees with your $display. None of these are tool bugs. They are consequences of the SystemVerilog stratified event scheduler — and once you can draw the region map, every one of them becomes predictable and preventable.

This topic walks a real race cycle by cycle, shows how clocking blocks eliminate it by construction, maps every scheduling region, and covers the controlled rule-breaking tools — hierarchical references and force/release — that let a testbench reach across the boundary safely.

Sub-topics

1. Anatomy of a TB/RTL Race — same-edge drive/sample race, cycle by cycle, and why it is nondeterministic.

2. Clocking Blocks as the Cure — input/output skew semantics and the same race re-walked with a cb.

3. Scheduling Regions: the Full Map — preponed through postponed, and where each kind of code runs.

4. Hierarchical References & Force/Release — xmr, force vs deposit, error injection, auditable usage.

5. Q&A: Races & Scheduling — interview-format answers with senior vs junior contrasts.

RTL/TB BOUNDARY — TOPIC MAP

            T E S T B E N C H                R T L
   ┌──────────────────────────┐    ┌────────────────────┐
   │ driver      monitor      │    │ always_ff blocks   │
   │   │            ▲         │    │ continuous assigns │
   └───┼────────────┼─────────┘    └─────────▲──────────┘
       │            │                        │
       ▼            │                        │
   [1] the race: who runs first at posedge? ─┘
       │
       ▼
   [2] clocking blocks: skewed sample/drive → race gone
       │
       ▼
   [3] scheduling regions: WHY it works
       (preponed → active → NBA → observed → reactive → postponed)
       │
       ▼
   [4] reaching across the boundary anyway:
       xmr · force/release · deposit  (controlled rule-breaking)
       │
       ▼
   [5] Q&A: explain all of it in an interview

Key takeaways

• TB/RTL races are scheduler-ordering ambiguities, not tool bugs — they are fully explainable.

• Clocking blocks remove drive/sample races by construction, not by luck.

• The region map (preponed → postponed) is the mental model behind every boundary behavior.