Review checklist

Review Checklist for Scenario: PLL Jitter Escalation focuses on timing margin loss from jitter, lock instability incidence, closure confidence. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

• Boundary assumptions are versioned and signed.

• Mode matrix (power/clock/reset/stress) is explicit.

• Physical context (floorplan/package/power) is included where relevant.

• Metric and artifact references are reproducible.

• Waivers have owner, expiry, and mitigation.

• Owners signed: clock owner, STA lead, bring-up owner.

Sign-off ownership

OWNERSHIP MAP — Scenario: PLL Jitter Escalation

artifact                  owner
----------------------    -----------------------------
integration artifact    clock owner
implementation artifact STA lead
signoff artifact        bring-up owner

Every boundary issue needs a named owner before fixes start.

AMS deep dive

Senior interview answers must show mechanism, ownership, and regression discipline.

Concept diagram

INTERVIEW LADDER

symptom -> mechanism -> evidence -> owner -> bounded fix -> regression

Metric graph

ANSWER QUALITY

mechanism depth ██████
evidence usage  █████
ownership clarity ████

Reports and artifacts

• mock interview rubric

• scenario response score

• evidence completeness

• regression-plan quality

Mini case study

Candidate fixed the symptom but failed to define a regression matrix and ownership map.

Debug branches

• Name first failing boundary

• State one proving artifact

• Propose one bounded reversible fix

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

PLL jitter excursions propagate into setup/hold uncertainty and link BER; root-cause isolation requires separating PLL loop behavior from supply/package contributors.

Metric: timing margin loss from jitter, lock instability incidence, closure confidence