Scenario: PLL Jitter Escalation: Debug Playbook

Debug playbook

Debug Playbook for Scenario: PLL Jitter Escalation focuses on timing margin loss from jitter, lock instability incidence, closure confidence. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

AMS debug is a hunt for first divergence, not downstream symptom management. Most costly delays come from wrong-owner first actions.

Root-cause tree

ROOT-CAUSE TREE — Scenario: PLL Jitter Escalation

timing margin loss from jitter, lock instability incidence, closure confidence regressed
        |
same silicon / run tags?
   /            \
 no              yes
 |                |
env mismatch    boundary contract or
tag mismatch    true physical issue
 /   \             |
clk   reset      isolate first failing
map   sequence   boundary transition

1. Freeze reproducer: mode, firmware/config, and evidence tags.

2. Find the first boundary signal that diverges.

3. Map divergence to contract clause and owner.

4. Classify failure: contract, sequencing, coupling, package, or tool-view mismatch.

5. Prove mechanism with one reduced reproducer.

6. Apply smallest reversible fix and rerun cross-domain regressions.

Review memo template

STAFF AMS REVIEW MEMO — AMS Interface Interview Prep / Scenario: PLL Jitter Escalation

1. Symptom
   - Watched metric: timing margin loss from jitter, lock instability incidence, closure confidence
   - Failing mode/condition: <power/clock/temp/workload>
   - Boundary under suspicion: <macro/wrapper/interface/lane/island>
   - Repro setup: <sim/emulation/lab + firmware/config tags>

2. Mechanism hypothesis
   - Primary mechanism: PLL jitter excursions propagate into setup/hold uncertainty and link BER; root-cause isolation requires separating PLL loop behavior from supply/package contributors.
   - Competing hypothesis: <contract gap, sequencing, physical coupling, package, tooling>
   - Missing evidence: <waveform, report, scope/analyzer capture, dashboard snapshot>

3. Proposed action
   - Minimal reversible change: <RTL/config/layout/policy>
   - Expected metric movement: <delta and conditions>
   - Regression risk: timing, noise, power, performance, compatibility

4. Signoff
   - Re-run artifact: jitter incident timeline, phase-noise report, correlated STA delta
   - Required owners: clock owner, STA lead, bring-up owner
   - Final decision: fix, waive with controls, or escalate

AMS deep dive

Senior interview answers must show mechanism, ownership, and regression discipline.

Concept diagram

INTERVIEW LADDER

symptom -> mechanism -> evidence -> owner -> bounded fix -> regression

Metric graph

ANSWER QUALITY

mechanism depth ██████
evidence usage  █████
ownership clarity ████

Reports and artifacts

• mock interview rubric

• scenario response score

• evidence completeness

• regression-plan quality

Mini case study

Candidate fixed the symptom but failed to define a regression matrix and ownership map.

Debug branches

• Name first failing boundary

• State one proving artifact

• Propose one bounded reversible fix

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

PLL jitter excursions propagate into setup/hold uncertainty and link BER; root-cause isolation requires separating PLL loop behavior from supply/package contributors.

Metric: timing margin loss from jitter, lock instability incidence, closure confidence