What evidence would convince you this is false sharing?

A busy coherence counter does not identify a source field. The method rests on the fourth C. The classic miss types are compulsory (first touch), capacity (the working set does not fit) and conflict (too many lines map to one set). A coherence miss is the fourth: the line was present, but another core's write invalidated it. Coherence misses split at word level. A miss is a true-sharing miss if the word now accessed was written by the other core since this cache lost the line. It is a false-sharing miss if that word was not written by the other core: the line moved only because a neighbouring word was written.

Two generic hardware events expose this. A hit-modified snoop response marks a local miss served from a line another cache holds in M: the data came cache to cache from a dirty copy, the Fwd-GetM case with C0 in M in the course model. It shows that a line is moving between writers, not which word moved it. Precise load/store sampling supplies the word: the core tags sampled memory instructions and records the exact data address, the core and whether the access was a hit-modified miss. Group the hit-modified samples by line (address // 64), then within each hot line by offset (address % 64) and by writing core.

The rule: several offsets in one line, written by different cores, is false sharing. One offset written by several cores is true sharing. In practice, name the target's documented event for the hit-modified response and for precise sampling before trusting either count.

Worked case on the X/Y schedule from Counting Coherence Traffic, sampled after the cold acquisition. Every steady-state store misses on a line the other core holds in M.

Keep input, operation count, core affinity and measured interval constant. Record both wall time and the miss counts. Without precise address samples, the hit-modified count alone cannot separate true from false sharing, so mark the attribution as incomplete.

Useful negative controls include a read-only phase, batched writes to the original layout, and the truly shared X variant. A read-only phase should not need repeated write-permission handoffs from these operations. Batching may improve the original layout without changing addresses. Padding should not remove the inherent sharing of one logical X.

A successful investigation ends with a narrow statement: independent fields in this phase caused avoidable line transfers, and the tested layout reduced those transfers while preserving results. It does not establish a universal speedup, a protocol bug, or a remedy for every coherence hotspot.

Related topics

• Shared course model

• Classify the sharing relationship