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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
    • False Sharing
    • Directory Capacity and Sharers
    • Hotspots and Placement
      • Hot Lines and Locks
      • Home Interleaving
      • NUMA and Locality
      • Scaling Trade-Off Exercise
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Hotspots and Placement
  1. Topics
  2. Cache Coherency
  3. Performance and Scalability
  4. Hotspots and Placement
  5. Home Interleaving

Part 7 · Performance and Scalability · All levels

Home Interleaving

Evaluate a selected line-address mapping without confusing home balance with cache-to-cache balance.

Why is one home busy while another is idle?

Extend H into two home instances H0 and H1, with exactly one selected home per line. C0/C1 remain the requesters. Compare two illustrative mappings of the line number, address // 64. The simple map, home = (address // 64) % 2, uses only bit 6 of the address. The parity hash, home = popcount(address // 64) % 2, XORs every line-number bit together. X at address 0 belongs to H0 under both. These are design exercises, not mappings attributed to any processor. Every conflict on X still goes to its one home.

Eight accesses

Lines touched

Simple map H0 / H1

Parity hash H0 / H1

Stride 64: 0, 64, ..., 448

0 to 7

4 / 4

4 / 4 (parities 0, 1, 1, 0, 1, 0, 0, 1)

Stride 128: 0, 128, ..., 896

0, 2, ..., 14

8 / 0: the stride never changes bit 6

4 / 4

Stride 256: 0, 256, ..., 1792

0, 4, ..., 28

8 / 0

4 / 4

Stride 192: 0, 192, ..., 1344

0, 3, ..., 21

4 / 4

7 / 1: popcounts 0, 2, 2, 2, 2, 4, 2, 3

Eight requests to X = 0

0 only

8 / 0

8 / 0: no address map splits one line

The parity hash fixes the 128- and 256-byte strides that alias the simple map, because a stride that never changes bit 6 still changes higher bits that the XOR includes. It is not stride-proof: stride 192 (three lines) gives an even popcount for seven of the eight lines, while the simple map balances it. Every fixed map has some pathological stride; a hash moves it to strides that are less common in real code. No map can spread a single hot line, because all its accesses share one line number.

example.py
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from collections import Counter
def mod2(address):
    return (address // 64) % 2              # bit 6 of the address
def parity(address):
    return bin(address // 64).count("1") % 2  # XOR of all line-number bits
def demand(home, stride, n=8):
    c = Counter(home(stride * i) for i in range(n))
    return (c[0], c[1])
for stride in (64, 128, 256):
    assert demand(parity, stride) == (4, 4)
assert demand(mod2, 64) == (4, 4)
assert demand(mod2, 128) == demand(mod2, 256) == (8, 0)
assert [bin(3 * i).count("1") for i in range(8)] == [0, 2, 2, 2, 2, 4, 2, 3]
assert demand(parity, 192) == (7, 1)    # a stride that defeats the hash
assert demand(mod2, 192) == (4, 4)      # but not the simple map
for home in (mod2, parity):
    assert Counter(home(0) for _ in range(8)) == {0: 8}  # one hot X
    assert home(0) == home(8) == home(63)  # one home per line
print("PASS: parity balances 64/128/256 strides but not 192, mod 2 the reverse, one hot X stays 8/0")
An illustrative address mapping selects one home per line, which orders conflicts and finds the current holder.
The home's address is a metadata destination, not necessarily the data source.

The count measures offered address demand, not service time. A balanced line count may still contain one expensive dirty intervention at one home and cheap hits at the other. Measure per-home queue occupancy, active time and request mix as well as request counts. Pending entries and finite completion buffers can be the limiting resource.

The mappings are compared as static choices fixed before traffic starts; changing one while lines are cached would need a separate migration protocol.

Common pitfall

Hashing byte offsets independently so two fields of one coherence line appear to have different homes.

Interview

Name a stride that defeats each map (128 for the simple map, 192 for the parity hash), then explain why balanced homes do not prove balanced links, DRAM banks or dirty-data sources.

Check yourself If C0 holds X M / 1 while memory = 0, where should H0 source a new reader's value?

It must resolve C0's current data through the selected protocol. Selecting H0 by address does not make memory current.

Related topics

  • Shared course model

  • Home capacity and admission

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See also

  • Scaling Trade-Off Exercise