CDC / RDC · All levels

Reset-aware Simulation: Review Checklist

Review Checklist for Reset-aware Simulation.

Review checklist

Review Checklist for Reset-aware Simulation focuses on reset scenario coverage, X-propagation escapes, boot repeatability. The goal is to convert issue observations into mechanism-backed closure decisions.

  • Crossing and reset intent are explicitly classified.

  • Protocol assumptions are documented and checked.

  • Critical issues have owners and dates.

  • Waivers include mechanism, containment, and expiry.

  • Regression matrix includes stress and milestone modes.

  • Owners signed: DV lead, RDC owner, firmware owner.

Signoff ownership

diagram
OWNERSHIP MAP — Reset-aware Simulation

artifact                  owner
----------------------    -------------------------
design intent           DV lead
verification evidence   RDC owner
signoff decision        firmware owner

Every open CDC/RDC issue needs one accountable owner before waiver or fix.

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

diagram
RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

diagram
MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

  • top-level RDC opens

  • reset simulation coverage

  • chip integration blockers

  • waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

  • Audit subsystem assumptions

  • stress chip-level reset scenarios

  • close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

  • State crossing class, assumptions, and owner with every issue.

  • Run structural and dynamic regressions after each fix.

Common pitfalls

  • Treating all warnings as equivalent risk.

  • Waiving issues without containment evidence.

  • Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Simulation with realistic reset jitter, sequencing, and asynchronous release uncovers scenarios that static analysis alone cannot classify.

Metric: reset scenario coverage, X-propagation escapes, boot repeatability