Reset-aware Simulation: Design Space

Design space exploration

For Reset-aware Simulation, signoff options trade reliability, latency, and schedule.

Option A — conservative

• Conservative synchronization: helps robustness

• Risk: latency increase

• Validate with: stress regressions

Option B — balanced

• Balanced protocol design: helps throughput + safety

• Risk: higher design effort

• Validate with: formal + simulation

Option C — aggressive

• Aggressive waiver posture: helps schedule relief

• Risk: escape risk

• Validate with: periodic waiver audit

Option D — refactor

• Architectural refactor: helps long-term safety

• Risk: schedule hit

• Validate with: system bring-up

DESIGN SPACE — Reset-aware Simulation
robustness <-> latency <-> complexity <-> schedule

Design pitfalls

• Waive-first behavior

• No owner for residual risk

Tradeoff curve

BEFORE / AFTER — Reset-aware Simulation

open critical issues
  ^
  |  o baseline
  |     o after fix batch
  |         o after protocol proof
  |             o signoff-ready
  +---------------------------------> closure iteration

Track issue burn-down with evidence quality, not only count.

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

• top-level RDC opens

• reset simulation coverage

• chip integration blockers

• waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

• Audit subsystem assumptions

• stress chip-level reset scenarios

• close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Simulation with realistic reset jitter, sequencing, and asynchronous release uncovers scenarios that static analysis alone cannot classify.

Metric: reset scenario coverage, X-propagation escapes, boot repeatability