CDC / RDC · All levels

Reset-aware Simulation: Reports & Metrics

Reports & Metrics for Reset-aware Simulation.

Reports and metrics

Reports & Metrics for Reset-aware Simulation focuses on reset scenario coverage, X-propagation escapes, boot repeatability. The goal is to convert issue observations into mechanism-backed closure decisions.

Reports must explain risk movement in reset scenario coverage, X-propagation escapes, boot repeatability, not just issue counts. A report is complete only when ownership and closure action are explicit.

Metric movement

diagram
METRIC TREND — reset scenario coverage, X-propagation escapes, boot repeatability

critical open issues
  ^
  |                target (0 critical)
  |              - - - - - - - - - -
  |          o post triage
  |      o initial run
  |   o baseline
  +--------------------------------------> review iteration

Always pair count trend with evidence quality trend.

Risk distribution

diagram
RISK HEATMAP — Reset-aware Simulation

severity
high   |  XX  X
medium |  XXX XX
low    |  XXX XXX
        +----------------------------> ownership readiness
         unassigned   in-progress   closed

Metric focus: reset scenario coverage, X-propagation escapes, boot repeatability
  • Track reset scenario coverage, X-propagation escapes, boot repeatability by block, mode, and severity.

  • Separate structural warnings from behavior-proven hazards.

  • Show waiver age and owner SLA alongside raw counts.

  • Store evidence links with each closure claim.

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

diagram
RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

diagram
MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

  • top-level RDC opens

  • reset simulation coverage

  • chip integration blockers

  • waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

  • Audit subsystem assumptions

  • stress chip-level reset scenarios

  • close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

  • State crossing class, assumptions, and owner with every issue.

  • Run structural and dynamic regressions after each fix.

Common pitfalls

  • Treating all warnings as equivalent risk.

  • Waiving issues without containment evidence.

  • Skipping reset and reconvergence stress after CDC fixes.

Reading evidence