DenseChip

CDC / RDC · All levels

Reset-aware Simulation: Step-by-Step Walkthrough

Step-by-Step Walkthrough for Reset-aware Simulation.

Step-by-step analysis walkthrough

Use this sequence when owning Reset-aware Simulation in a signoff review.

  1. Inspect warning class and severity.

  2. Trace crossing endpoints and domains.

  3. Check protocol/reset assumptions against spec.

  4. Review synchronizer or FIFO implementation detail.

  5. Run focused assertion or formal check.

  6. Draft fix options with risk and schedule impact.

  7. Execute regression and publish closure memo.

Artifacts to collect

  • reset stress testbench, X-prop report, scenario coverage table

  • crossing inventory

  • waiver board notes

  • regression report

Decision memo template

diagram
CDC/RDC DECISION MEMO — Reset-aware Simulation
risk class:
mechanism:
evidence:
fix/waiver:
owners: DV lead, RDC owner, firmware owner

Reference visuals

Reset stress envelope

diagram
vary:
  - reset pulse width
  - release skew per domain
  - clock start phase
  - power-up ordering

Observe X-prop and functional convergence.

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

diagram
RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

diagram
MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

  • top-level RDC opens

  • reset simulation coverage

  • chip integration blockers

  • waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

  • Audit subsystem assumptions

  • stress chip-level reset scenarios

  • close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

  • State crossing class, assumptions, and owner with every issue.

  • Run structural and dynamic regressions after each fix.

Common pitfalls

  • Treating all warnings as equivalent risk.

  • Waiving issues without containment evidence.

  • Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Simulation with realistic reset jitter, sequencing, and asynchronous release uncovers scenarios that static analysis alone cannot classify.

Metric: reset scenario coverage, X-propagation escapes, boot repeatability

Practice this lesson