Reset-aware Simulation: Worked Example

Worked example

Worked Example for Reset-aware Simulation focuses on reset scenario coverage, X-propagation escapes, boot repeatability. The goal is to convert issue observations into mechanism-backed closure decisions.

A milestone review shows reset scenario coverage, X-propagation escapes, boot repeatability. Teams disagree on severity. The right move is to isolate one representative issue, prove mechanism class, and decide fix or waiver with explicit residual risk.

Crossing under inspection

CROSSING FLOW — Reset-aware Simulation

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: reset scenario coverage, X-propagation escapes, boot repeatability

Reset stress envelope

vary:
  - reset pulse width
  - release skew per domain
  - clock start phase
  - power-up ordering

Observe X-prop and functional convergence.

1. Capture warning, waveform, and owning module context.

2. Tag mode/reset/traffic state for the failure.

3. Validate assumptions against spec and assertions.

4. Compare outcome with reset stress testbench, X-prop report, scenario coverage table.

5. Choose one reversible action and define regression upfront.

Did the action work?

BEFORE / AFTER — Reset-aware Simulation

open critical issues
  ^
  |  o baseline
  |     o after fix batch
  |         o after protocol proof
  |             o signoff-ready
  +---------------------------------> closure iteration

Track issue burn-down with evidence quality, not only count.

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

• top-level RDC opens

• reset simulation coverage

• chip integration blockers

• waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

• Audit subsystem assumptions

• stress chip-level reset scenarios

• close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Simulation with realistic reset jitter, sequencing, and asynchronous release uncovers scenarios that static analysis alone cannot classify.

Metric: reset scenario coverage, X-propagation escapes, boot repeatability