DDR PHY, Training & Signal Integrity

Section goal

DQ/DQS strobes, write leveling, read training, Vref, eye margins, package/channel effects, and high-speed PHY bring-up.

This section trains how to reason from traffic behavior to DRAM mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

1. Start with each topic hub and draw the mechanism path.

2. Use reports and debug pages to prove causality before tuning.

3. Practice worked examples and interview drills with explicit evidence chains.

4. Close each topic with checklist and silicon impact pages.

Topics

1. dq-dqs-strobes-and-capture/ - DQ/DQS Strobes and Data Capture Windows

2. write-leveling-read-training/ - Write Leveling and Read Training Sequence Design

3. vref-eye-margin-and-calibration/ - Vref, Eye Margin, and Calibration Closure

4. channel-si-pi-and-package-effects/ - Channel SI/PI and Package Effects on PHY Bring-Up

Related topics

• DRAM & Memory Design course hub

DRAM deep dive

PHY training quality sets real timing margin through write leveling, read gate alignment, and Vref calibration.

Concept diagram

DDR PHY TRAINING FLOW

write leveling -> read gate -> per-bit deskew -> Vref calibration -> margin validate

Metric graph

MARGIN EROSION SOURCES

channel skew drift    █████
voltage/temperature   ████
board SI noise        ███

Reports and artifacts

• training margin histogram

• DQ/DQS skew log

• Vref sweep report

• retrain trigger incident timeline

Mini case study

A board spin passed cold boot but failed warm retrain due to narrowed DQ eye margins on one byte lane.

Debug branches

• Compare byte-lane margins across thermal corners

• Correlate retrain events with power-state transitions

• Confirm SI fixes before loosening PHY timing guards

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?