Leakage Recovery

What this topic teaches

Leakage Recovery teaches how to turn synthesis intent into stable QoR outcomes. Leakage recovery replaces fast cells with higher-VT alternatives while preserving margin on critical paths and corners. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When leakage delta, WNS guardband consumed, swapped-cell count moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

SYNTHESIS FLOW — Leakage Recovery

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: leakage delta, WNS guardband consumed, swapped-cell count

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Leakage recovery pass

timing-safe cells
  -> swap to higher VT
  -> re-check setup/hold
  -> keep only safe swaps

QoR trend shape

QOR TREND — Leakage Recovery

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: leakage delta, WNS guardband consumed, swapped-cell count

Who owns which layer

SYNTHESIS OWNERSHIP LAYERS — Leakage Recovery

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

• Primary metric: leakage delta, WNS guardband consumed, swapped-cell count.

• Primary artifact: leakage recovery report, swap list, hold/setup regression report.

• Owners to involve: power owner, synthesis owner, STA owner.

• One baseline run and one regressed run with matching manifests.

• A rollback-safe change proposal with full regression scope.

Ownership map

OWNERSHIP MAP — Leakage Recovery

artifact              owner
----------------      -----------------
compile owner       power owner
timing/power owner  synthesis owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Always present QoR with run context and artifact.

• Prefer reversible fixes with explicit rollback criteria.

• Re-run timing, area, and power checks before closing.

Common pitfalls

• Comparing unlike compile contexts.

• Timing-only wins that worsen power or area.

• Skipping equivalence checks after structural changes.

Synthesis deep dive

PPA closure is a constrained tradeoff problem, not a timing-only exercise.

Concept diagram

PPA TRIAD

timing target <-> power budget <-> area cap

Metric graph

PARETO PROGRESSION

early runs      o o
balanced point    o
over-tuned          o (risk)

Reports and artifacts

• VT mix

• leakage trend

• dynamic power trend

• PPA Pareto table

Mini case study

LVT-heavy fix recovered setup but violated leakage target; balanced VT strategy closed both.

Debug branches

• Timing-only claims need power check

• Validate hold on VT swaps

• Use Pareto memo

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.