Synthesis & Logic Optimization · All levels

Leakage Recovery: Inputs & Outputs

Inputs & Outputs for Leakage Recovery.

Inputs and outputs contract

Inputs & Outputs for Leakage Recovery focuses on leakage delta, WNS guardband consumed, swapped-cell count. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis closure fails when teams optimize against different assumptions. Treat these artifacts as a signed handoff contract.

diagram
INPUTS
  - RTL tag and compile switches
  - SDC / policy constraints
  - Library and operating views
  - Optional physical estimates (topo/congestion)

OUTPUTS
  - QoR timing/area/power reports
  - transform/mapping summaries
  - owner-tagged closure memo
  - regression matrix verdict

Flow sequence

diagram
SYNTHESIS FLOW — Leakage Recovery

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: leakage delta, WNS guardband consumed, swapped-cell count

Ownership map

diagram
OWNERSHIP MAP — Leakage Recovery

artifact              owner
----------------      -----------------
compile owner       power owner
timing/power owner  synthesis owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

PPA closure is a constrained tradeoff problem, not a timing-only exercise.

Concept diagram

diagram
PPA TRIAD

timing target <-> power budget <-> area cap

Metric graph

diagram
PARETO PROGRESSION

early runs      o o
balanced point    o
over-tuned          o (risk)

Reports and artifacts

  • VT mix

  • leakage trend

  • dynamic power trend

  • PPA Pareto table

Mini case study

LVT-heavy fix recovered setup but violated leakage target; balanced VT strategy closed both.

Debug branches

  • Timing-only claims need power check

  • Validate hold on VT swaps

  • Use Pareto memo

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

  • State exact run context (RTL, SDC, libs, switches) with every QoR claim.

  • Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

  • Comparing runs with mismatched constraints or library views.

  • Timing-only fixes that violate power or area budgets.

  • Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Leakage recovery replaces fast cells with higher-VT alternatives while preserving margin on critical paths and corners.

Metric: leakage delta, WNS guardband consumed, swapped-cell count