Synthesis & Logic Optimization · All levels

VT Mix Strategy: Review Checklist

Review Checklist for VT Mix Strategy.

Review checklist

Review Checklist for VT Mix Strategy focuses on HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

  • Run manifest is attached (RTL/SDC/libs/switches).

  • Primary metric and impacted lane are named.

  • Mechanism hypothesis is evidence-backed.

  • Fix is reversible and owner-assigned.

  • Regression matrix includes timing, area, power, and equivalence as needed.

  • Owners signed: synthesis owner, power owner, STA owner.

Sign-off ownership

diagram
OWNERSHIP MAP — VT Mix Strategy

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  power owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

PPA closure is a constrained tradeoff problem, not a timing-only exercise.

Concept diagram

diagram
PPA TRIAD

timing target <-> power budget <-> area cap

Metric graph

diagram
PARETO PROGRESSION

early runs      o o
balanced point    o
over-tuned          o (risk)

Reports and artifacts

  • VT mix

  • leakage trend

  • dynamic power trend

  • PPA Pareto table

Mini case study

LVT-heavy fix recovered setup but violated leakage target; balanced VT strategy closed both.

Debug branches

  • Timing-only claims need power check

  • Validate hold on VT swaps

  • Use Pareto memo

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

  • State exact run context (RTL, SDC, libs, switches) with every QoR claim.

  • Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

  • Comparing runs with mismatched constraints or library views.

  • Timing-only fixes that violate power or area budgets.

  • Skipping equivalence checks after structural changes.

Principal synthesis review addendum

VT assignment trades delay against leakage; poor mix causes either timing misses or unnecessary static power burn.

Metric: HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget