VT Mix Strategy: Software / Programmer View

RTL / implementation view

Activity profile and architecture choices constrain dynamic power opportunities.

What designers feel

• QoR sensitivity to small RTL edits

• Unexpected retiming blockers

• Clock-gating mismatch

RTL structure impact

• Pipeline boundaries

• Enable semantics

• Hierarchy and attributes

Synthesis interaction

• Compile effort knobs

• Retiming permissions

• Preserve policy scope

RTL-side mitigations

• Constraint/code co-review

• Stable naming for ECO

• Formal-first posture

RTL -> synthesis check for VT Mix Strategy
// verify mapping intent before compile signoff

Layer the designer touches

SYNTHESIS OWNERSHIP LAYERS — VT Mix Strategy

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Synthesis deep dive

PPA closure is a constrained tradeoff problem, not a timing-only exercise.

Concept diagram

PPA TRIAD

timing target <-> power budget <-> area cap

Metric graph

PARETO PROGRESSION

early runs      o o
balanced point    o
over-tuned          o (risk)

Reports and artifacts

• VT mix

• leakage trend

• dynamic power trend

• PPA Pareto table

Mini case study

LVT-heavy fix recovered setup but violated leakage target; balanced VT strategy closed both.

Debug branches

• Timing-only claims need power check

• Validate hold on VT swaps

• Use Pareto memo

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

VT assignment trades delay against leakage; poor mix causes either timing misses or unnecessary static power burn.

Metric: HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget