VT Mix Strategy: Worked Example

Worked example

Worked Example for VT Mix Strategy focuses on HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

A weekly compile reports HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget regression. Instead of random knob tuning, start by proving whether input context changed and which mechanism dominates.

Sequence under inspection

SYNTHESIS FLOW — VT Mix Strategy

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget

VT mix triangle

LVT: speed ++ leakage --
SVT: balance
HVT: speed -- leakage ++

mix per criticality bucket

1. Capture baseline and regressed artifact pair.

2. Confirm manifest parity (RTL, SDC, libs, switches).

3. Pin first metric drift and mechanism hypothesis.

4. Reproduce with VT distribution report, leakage breakdown, timing split report.

5. Apply one reversible fix and run matrix regression.

Did the fix hold?

BEFORE / AFTER QOR — VT Mix Strategy

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

PPA closure is a constrained tradeoff problem, not a timing-only exercise.

Concept diagram

PPA TRIAD

timing target <-> power budget <-> area cap

Metric graph

PARETO PROGRESSION

early runs      o o
balanced point    o
over-tuned          o (risk)

Reports and artifacts

• VT mix

• leakage trend

• dynamic power trend

• PPA Pareto table

Mini case study

LVT-heavy fix recovered setup but violated leakage target; balanced VT strategy closed both.

Debug branches

• Timing-only claims need power check

• Validate hold on VT swaps

• Use Pareto memo

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

VT assignment trades delay against leakage; poor mix causes either timing misses or unnecessary static power burn.

Metric: HVT/SVT/LVT cell mix, setup/hold slack distribution, leakage budget