Clock-Gating Inference

What this topic teaches

Clock-Gating Inference teaches how to turn synthesis intent into stable QoR outcomes. Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When clock-gating insertion rate, gating check violations, clock power delta moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

SYNTHESIS FLOW — Clock-Gating Inference

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: clock-gating insertion rate, gating check violations, clock power delta

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Clock-gating insertion loop

RTL enable intent
      |
      v
gating inference rules
      |
      v
insert ICG cells + checks
      |
      v
power delta + gating-safe verification

QoR trend shape

QOR TREND — Clock-Gating Inference

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: clock-gating insertion rate, gating check violations, clock power delta

Who owns which layer

SYNTHESIS OWNERSHIP LAYERS — Clock-Gating Inference

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

• Primary metric: clock-gating insertion rate, gating check violations, clock power delta.

• Primary artifact: clock-gating report, enable-condition review, power comparison.

• Owners to involve: synthesis owner, power owner, verification owner.

• One baseline run and one regressed run with matching manifests.

• A rollback-safe change proposal with full regression scope.

Ownership map

OWNERSHIP MAP — Clock-Gating Inference

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  power owner
cross-team review   verification owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Always present QoR with run context and artifact.

• Prefer reversible fixes with explicit rollback criteria.

• Re-run timing, area, and power checks before closing.

Common pitfalls

• Comparing unlike compile contexts.

• Timing-only wins that worsen power or area.

• Skipping equivalence checks after structural changes.

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

• compile QoR

• unconstrained endpoints

• constraint lint

• policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

• Diff SDC first

• Audit dont_touch scope

• Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.