Clock-Gating Inference: Review Checklist

Review checklist

Review Checklist for Clock-Gating Inference focuses on clock-gating insertion rate, gating check violations, clock power delta. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

• Run manifest is attached (RTL/SDC/libs/switches).

• Primary metric and impacted lane are named.

• Mechanism hypothesis is evidence-backed.

• Fix is reversible and owner-assigned.

• Regression matrix includes timing, area, power, and equivalence as needed.

• Owners signed: synthesis owner, power owner, verification owner.

Sign-off ownership

OWNERSHIP MAP — Clock-Gating Inference

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  power owner
cross-team review   verification owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

• compile QoR

• unconstrained endpoints

• constraint lint

• policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

• Diff SDC first

• Audit dont_touch scope

• Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating.

Metric: clock-gating insertion rate, gating check violations, clock power delta