Synthesis & Logic Optimization · All levels

Clock-Gating Inference: Debug Playbook

Debug Playbook for Clock-Gating Inference.

Debug playbook

Debug Playbook for Clock-Gating Inference focuses on clock-gating insertion rate, gating check violations, clock power delta. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis debug finds the first causal drift, not the loudest downstream symptom.

Root-cause tree

diagram

ROOT-CAUSE TREE — Clock-Gating Inference

clock-gating insertion rate, gating check violations, clock power delta regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

Freeze baseline and regressed run manifests.
Verify RTL/SDC/library deltas before transform tuning.
Classify issue: constraints, mapping choice, physical estimate, or ECO side effect.
Pick one minimal reversible change.
Re-run full timing/area/power checks with ownership signoff.

Review memo template

diagram

STAFF SYNTHESIS REVIEW MEMO — Constraints & QoR / Clock-Gating Inference

1. Symptom
   - Watched metric: clock-gating insertion rate, gating check violations, clock power delta
   - Affected compile run: <tag/build ID>
   - Impacted path/class: <critical group / power lane / area lane>
   - Database tags: <RTL, SDC, libs, switches>

2. Mechanism hypothesis
   - Primary mechanism: Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating.
   - Competing hypothesis: <constraint drift, mapping choice, physical estimate mismatch>
   - Missing evidence: <report diff, dashboard trend, ownership board>

3. Proposed action
   - Minimal reversible change: <constraint patch, compile knob, ECO cell move>
   - Expected movement: <timing / area / power delta>
   - Regression risk: hold, power spike, leakage drift, formal mismatch

4. Signoff
   - Re-run artifact: clock-gating report, enable-condition review, power comparison
   - Required owners: synthesis owner, power owner, verification owner
   - Final decision: merge, rollback, or escalate

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

diagram

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

compile QoR
unconstrained endpoints
constraint lint
policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

Diff SDC first
Audit dont_touch scope
Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating.

Metric: clock-gating insertion rate, gating check violations, clock power delta

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