Clock-Gating Inference: Interview Drills

Interview drills

Interview Drills for Clock-Gating Inference focuses on clock-gating insertion rate, gating check violations, clock power delta. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

PROMPT
You observe clock-gating insertion rate, gating check violations, clock power delta in Clock-Gating Inference. Walk through root cause and closure plan.

STRONG ANSWER
1. Names run context and affected QoR lane.
2. Explains Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating.
3. Requests clock-gating report, enable-condition review, power comparison.
4. Proposes one reversible fix and full regression scope.

WEAK ANSWER
Jumps to random tool switches without mechanism evidence.

Whiteboard diagram

Clock-gating insertion loop

RTL enable intent
      |
      v
gating inference rules
      |
      v
insert ICG cells + checks
      |
      v
power delta + gating-safe verification

Root-cause narration

ROOT-CAUSE TREE — Clock-Gating Inference

clock-gating insertion rate, gating check violations, clock power delta regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

• compile QoR

• unconstrained endpoints

• constraint lint

• policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

• Diff SDC first

• Audit dont_touch scope

• Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating.

Metric: clock-gating insertion rate, gating check violations, clock power delta