Clock-Gating Inference: Worked Example

Worked example

Worked Example for Clock-Gating Inference focuses on clock-gating insertion rate, gating check violations, clock power delta. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

A weekly compile reports clock-gating insertion rate, gating check violations, clock power delta regression. Instead of random knob tuning, start by proving whether input context changed and which mechanism dominates.

Sequence under inspection

SYNTHESIS FLOW — Clock-Gating Inference

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: clock-gating insertion rate, gating check violations, clock power delta

Clock-gating insertion loop

RTL enable intent
      |
      v
gating inference rules
      |
      v
insert ICG cells + checks
      |
      v
power delta + gating-safe verification

1. Capture baseline and regressed artifact pair.

2. Confirm manifest parity (RTL, SDC, libs, switches).

3. Pin first metric drift and mechanism hypothesis.

4. Reproduce with clock-gating report, enable-condition review, power comparison.

5. Apply one reversible fix and run matrix regression.

Did the fix hold?

BEFORE / AFTER QOR — Clock-Gating Inference

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

• compile QoR

• unconstrained endpoints

• constraint lint

• policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

• Diff SDC first

• Audit dont_touch scope

• Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Inference quality depends on RTL style and constraints; wrong enable semantics or exclusion policy causes either missed savings or unsafe gating.

Metric: clock-gating insertion rate, gating check violations, clock power delta