Synthesis SDC Contracts: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Synthesis SDC Contracts focuses on compile WNS/TNS, unconstrained endpoint count, SDC lint error rate. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis closure fails when teams optimize against different assumptions. Treat these artifacts as a signed handoff contract.

INPUTS
  - RTL tag and compile switches
  - SDC / policy constraints
  - Library and operating views
  - Optional physical estimates (topo/congestion)

OUTPUTS
  - QoR timing/area/power reports
  - transform/mapping summaries
  - owner-tagged closure memo
  - regression matrix verdict

Flow sequence

SYNTHESIS FLOW — Synthesis SDC Contracts

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: compile WNS/TNS, unconstrained endpoint count, SDC lint error rate

Ownership map

OWNERSHIP MAP — Synthesis SDC Contracts

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  STA owner
cross-team review   RTL owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

• compile QoR

• unconstrained endpoints

• constraint lint

• policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

• Diff SDC first

• Audit dont_touch scope

• Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Synthesis SDC defines clocks, IO assumptions, and optimization boundaries; weak constraints produce fake QoR wins and expensive downstream churn.

Metric: compile WNS/TNS, unconstrained endpoint count, SDC lint error rate