Synthesis & Logic Optimization · All levels

Synthesis SDC Contracts: Mechanism

Mechanism for Synthesis SDC Contracts.

Mechanism to understand

Mechanism for Synthesis SDC Contracts focuses on compile WNS/TNS, unconstrained endpoint count, SDC lint error rate. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis SDC defines clocks, IO assumptions, and optimization boundaries; weak constraints produce fake QoR wins and expensive downstream churn. Treat synthesis as a contract: constraints + transforms + reports must agree.

  • Identify which lane moved first: timing, area, power, or runtime.

  • Identify whether drift is input, transform, or correlation related.

  • Identify owner before applying any ECO.

Flow model

diagram
SYNTHESIS FLOW — Synthesis SDC Contracts

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: compile WNS/TNS, unconstrained endpoint count, SDC lint error rate

Synthesis constraint contract

diagram
SDC CONTRACT

create_clock / generated_clock
set_input_delay / set_output_delay
exceptions (false/multicycle, audited)
compile QoR + unconstrained path report

Bad contract => misleading QoR.

Layer responsibilities

diagram
SYNTHESIS OWNERSHIP LAYERS — Synthesis SDC Contracts

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

diagram
CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

diagram
QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

  • compile QoR

  • unconstrained endpoints

  • constraint lint

  • policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

  • Diff SDC first

  • Audit dont_touch scope

  • Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

  • State exact run context (RTL, SDC, libs, switches) with every QoR claim.

  • Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

  • Comparing runs with mismatched constraints or library views.

  • Timing-only fixes that violate power or area budgets.

  • Skipping equivalence checks after structural changes.

Mechanism deep dive

Synthesis SDC defines clocks, IO assumptions, and optimization boundaries; weak constraints produce fake QoR wins and expensive downstream churn.