Synthesis SDC Contracts: Pitfalls & Red Flags

Pitfalls and red flags

Pitfalls & Red Flags for Synthesis SDC Contracts focuses on compile WNS/TNS, unconstrained endpoint count, SDC lint error rate. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

• Dashboard trend breaks without recorded manifest changes.

• dont_touch list grows without periodic removal review.

• Retiming gains claimed without formal evidence.

• Topographical numbers treated as final signoff.

• Fix improves one lane but silently regresses another.

Layer responsibility check

SYNTHESIS OWNERSHIP LAYERS — Synthesis SDC Contracts

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Synthesis deep dive

Constraint hygiene determines whether synthesis QoR is trustworthy.

Concept diagram

CONSTRAINT FLOW

RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gate

Metric graph

QOR HEALTH

constraint lint pass   ███████████████
unconstrained count    ███
policy violations      ██

Reports and artifacts

• compile QoR

• unconstrained endpoints

• constraint lint

• policy audit log

Mini case study

Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.

Debug branches

• Diff SDC first

• Audit dont_touch scope

• Track unconstrained trend weekly

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Synthesis SDC defines clocks, IO assumptions, and optimization boundaries; weak constraints produce fake QoR wins and expensive downstream churn.

Metric: compile WNS/TNS, unconstrained endpoint count, SDC lint error rate