Synthesis & Logic Optimization · All levels
Synthesis SDC Contracts: Step-by-Step Walkthrough
Step-by-Step Walkthrough for Synthesis SDC Contracts.
Step-by-step analysis walkthrough
Use when you own Synthesis SDC Contracts in a synthesis closure review.
Confirm exact run context (RTL/SDC/lib/switch set).
Open section QoR dashboard and identify first drift.
Inspect topic-level report for mechanism evidence.
Determine owner and candidate reversible action.
Apply one change only; avoid bundled fixes.
Run full timing/area/power checks.
Validate side effects on neighboring path groups.
Publish memo with outcome and residual risk.
Artifacts to collect
compile report, SDC lint log, unconstrained path report
QoR dashboard
run manifest
constraint diff
regression matrix
Decision memo template
SYNTHESIS DECISION MEMO — Synthesis SDC Contracts
run context:
observed metric:
hypothesis:
fix:
regression:
owners: synthesis owner, STA owner, RTL ownerReference visuals
Synthesis constraint contract
SDC CONTRACT
create_clock / generated_clock
set_input_delay / set_output_delay
exceptions (false/multicycle, audited)
compile QoR + unconstrained path report
Bad contract => misleading QoR.Synthesis deep dive
Constraint hygiene determines whether synthesis QoR is trustworthy.
Concept diagram
CONSTRAINT FLOW
RTL intent -> synthesis SDC -> compile checks -> QoR dashboard -> review gateMetric graph
QOR HEALTH
constraint lint pass ███████████████
unconstrained count ███
policy violations ██Reports and artifacts
compile QoR
unconstrained endpoints
constraint lint
policy audit log
Mini case study
Nightly WNS improved but unconstrained paths jumped; strict SDC lint restored true QoR picture.
Debug branches
Diff SDC first
Audit dont_touch scope
Track unconstrained trend weekly
Senior review question
Ask: what evidence proves this QoR move is real and stable?
Key takeaways
State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.
Common pitfalls
Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.
Principal synthesis review addendum
Synthesis SDC defines clocks, IO assumptions, and optimization boundaries; weak constraints produce fake QoR wins and expensive downstream churn.
Metric: compile WNS/TNS, unconstrained endpoint count, SDC lint error rate