Pipeline Tradeoffs: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Pipeline Tradeoffs focuses on latency cycles, throughput target hit rate, WNS improvement per stage. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis closure fails when teams optimize against different assumptions. Treat these artifacts as a signed handoff contract.

INPUTS
  - RTL tag and compile switches
  - SDC / policy constraints
  - Library and operating views
  - Optional physical estimates (topo/congestion)

OUTPUTS
  - QoR timing/area/power reports
  - transform/mapping summaries
  - owner-tagged closure memo
  - regression matrix verdict

Flow sequence

SYNTHESIS FLOW — Pipeline Tradeoffs

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: latency cycles, throughput target hit rate, WNS improvement per stage

Ownership map

OWNERSHIP MAP — Pipeline Tradeoffs

artifact              owner
----------------      -----------------
compile owner       microarchitecture owner
timing/power owner  RTL owner
cross-team review   synthesis lead

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Datapath and retiming gains are only real if formal and timing remain clean.

Concept diagram

DATAPATH + RETIME

operator inference -> stage balancing -> formal proof -> QoR validation

Metric graph

FREQUENCY VS LATENCY

Fmax gain   ████████
latency cost ████

Reports and artifacts

• retiming report

• datapath inference log

• equivalence status

• latency impact sheet

Mini case study

Retiming met frequency target, but missing formal hooks delayed closure by two days.

Debug branches

• Check retime blockers

• Formal first for aggressive moves

• Compare with pipeline option

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Pipeline changes trade latency for frequency and area; strong teams quantify benefit versus verification and microarchitecture cost.

Metric: latency cycles, throughput target hit rate, WNS improvement per stage