Pipeline Tradeoffs: Worked Example

Worked example

Worked Example for Pipeline Tradeoffs focuses on latency cycles, throughput target hit rate, WNS improvement per stage. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

A weekly compile reports latency cycles, throughput target hit rate, WNS improvement per stage regression. Instead of random knob tuning, start by proving whether input context changed and which mechanism dominates.

Sequence under inspection

SYNTHESIS FLOW — Pipeline Tradeoffs

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: latency cycles, throughput target hit rate, WNS improvement per stage

Pipeline decision plane

more stages -> better Fmax
more stages -> higher latency + verification cost
pick based on product constraints

1. Capture baseline and regressed artifact pair.

2. Confirm manifest parity (RTL, SDC, libs, switches).

3. Pin first metric drift and mechanism hypothesis.

4. Reproduce with pipeline option matrix, latency budget, closure comparison.

5. Apply one reversible fix and run matrix regression.

Did the fix hold?

BEFORE / AFTER QOR — Pipeline Tradeoffs

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Datapath and retiming gains are only real if formal and timing remain clean.

Concept diagram

DATAPATH + RETIME

operator inference -> stage balancing -> formal proof -> QoR validation

Metric graph

FREQUENCY VS LATENCY

Fmax gain   ████████
latency cost ████

Reports and artifacts

• retiming report

• datapath inference log

• equivalence status

• latency impact sheet

Mini case study

Retiming met frequency target, but missing formal hooks delayed closure by two days.

Debug branches

• Check retime blockers

• Formal first for aggressive moves

• Compare with pipeline option

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Pipeline changes trade latency for frequency and area; strong teams quantify benefit versus verification and microarchitecture cost.

Metric: latency cycles, throughput target hit rate, WNS improvement per stage