Synthesis & Logic Optimization · All levels

Retiming Fundamentals

Datapath & Retiming: Retiming moves registers across combinational logic to rebalance stage delay while preserving functionality under reset and enable constraints.

What this topic teaches

Retiming Fundamentals teaches how to turn synthesis intent into stable QoR outcomes. Retiming moves registers across combinational logic to rebalance stage delay while preserving functionality under reset and enable constraints. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When retimed register count, critical path depth change, equivalence pass rate moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

diagram

SYNTHESIS FLOW — Retiming Fundamentals

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: retimed register count, critical path depth change, equivalence pass rate

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Retiming move

diagram

FF -> combinational -> FF
can become
comb -> FF -> comb -> FF

Goal: rebalance stage delay.

QoR trend shape

diagram

QOR TREND — Retiming Fundamentals

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: retimed register count, critical path depth change, equivalence pass rate

Who owns which layer

diagram

SYNTHESIS OWNERSHIP LAYERS — Retiming Fundamentals

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

Primary metric: retimed register count, critical path depth change, equivalence pass rate.
Primary artifact: retiming report, stage-depth histogram, equivalence log.
Owners to involve: synthesis owner, formal owner, STA owner.
One baseline run and one regressed run with matching manifests.
A rollback-safe change proposal with full regression scope.

Ownership map

diagram

OWNERSHIP MAP — Retiming Fundamentals

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  formal owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

Always present QoR with run context and artifact.
Prefer reversible fixes with explicit rollback criteria.
Re-run timing, area, and power checks before closing.

Common pitfalls

Comparing unlike compile contexts.
Timing-only wins that worsen power or area.
Skipping equivalence checks after structural changes.

Synthesis deep dive

Datapath and retiming gains are only real if formal and timing remain clean.

Concept diagram

diagram

DATAPATH + RETIME

operator inference -> stage balancing -> formal proof -> QoR validation

Metric graph

diagram

FREQUENCY VS LATENCY

Fmax gain   ████████
latency cost ████

Reports and artifacts

retiming report
datapath inference log
equivalence status
latency impact sheet

Mini case study

Retiming met frequency target, but missing formal hooks delayed closure by two days.

Debug branches

Check retime blockers
Formal first for aggressive moves
Compare with pipeline option

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.

Practice this lesson