Retiming Fundamentals: Review Checklist

Review checklist

Review Checklist for Retiming Fundamentals focuses on retimed register count, critical path depth change, equivalence pass rate. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

• Run manifest is attached (RTL/SDC/libs/switches).

• Primary metric and impacted lane are named.

• Mechanism hypothesis is evidence-backed.

• Fix is reversible and owner-assigned.

• Regression matrix includes timing, area, power, and equivalence as needed.

• Owners signed: synthesis owner, formal owner, STA owner.

Sign-off ownership

OWNERSHIP MAP — Retiming Fundamentals

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  formal owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Datapath and retiming gains are only real if formal and timing remain clean.

Concept diagram

DATAPATH + RETIME

operator inference -> stage balancing -> formal proof -> QoR validation

Metric graph

FREQUENCY VS LATENCY

Fmax gain   ████████
latency cost ████

Reports and artifacts

• retiming report

• datapath inference log

• equivalence status

• latency impact sheet

Mini case study

Retiming met frequency target, but missing formal hooks delayed closure by two days.

Debug branches

• Check retime blockers

• Formal first for aggressive moves

• Compare with pipeline option

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Retiming moves registers across combinational logic to rebalance stage delay while preserving functionality under reset and enable constraints.

Metric: retimed register count, critical path depth change, equivalence pass rate