Synthesis & Logic Optimization · All levels

ECO Netlist Patches

Incremental & ECO Synthesis: ECO patching edits gate-level logic for urgent fixes; patch quality depends on locality, observability, and verification closure.

What this topic teaches

ECO Netlist Patches teaches how to turn synthesis intent into stable QoR outcomes. ECO patching edits gate-level logic for urgent fixes; patch quality depends on locality, observability, and verification closure. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When patch count, setup/hold recovery, patch-induced side effects moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

diagram
SYNTHESIS FLOW — ECO Netlist Patches

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: patch count, setup/hold recovery, patch-induced side effects

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Netlist patch loop

diagram
failing path -> patch cell/net
          -> re-run timing
          -> run equivalence
          -> merge or rollback

QoR trend shape

diagram
QOR TREND — ECO Netlist Patches

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: patch count, setup/hold recovery, patch-induced side effects

Who owns which layer

diagram
SYNTHESIS OWNERSHIP LAYERS — ECO Netlist Patches

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

  • Primary metric: patch count, setup/hold recovery, patch-induced side effects.

  • Primary artifact: netlist diff, ECO patch log, post-patch timing report.

  • Owners to involve: synthesis owner, STA owner, formal owner.

  • One baseline run and one regressed run with matching manifests.

  • A rollback-safe change proposal with full regression scope.

Ownership map

diagram
OWNERSHIP MAP — ECO Netlist Patches

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  STA owner
cross-team review   formal owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

  • Always present QoR with run context and artifact.

  • Prefer reversible fixes with explicit rollback criteria.

  • Re-run timing, area, and power checks before closing.

Common pitfalls

  • Comparing unlike compile contexts.

  • Timing-only wins that worsen power or area.

  • Skipping equivalence checks after structural changes.

Synthesis deep dive

Incremental and ECO synthesis protect schedule only with strict regression discipline.

Concept diagram

diagram
INCREMENTAL ECO LOOP

identify delta -> localized compile -> patch -> regression -> release

Metric graph

diagram
ECO CYCLE TIME

full compile      ███████████
incremental       █████

Reports and artifacts

  • incremental reuse

  • ECO patch list

  • LEC status

  • regression matrix

Mini case study

Localized compile cut turnaround 40%, but skipped LEC caused rollback.

Debug branches

  • Reuse ratio is not enough

  • Patch locality check

  • Always include equivalence hooks

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

  • State exact run context (RTL, SDC, libs, switches) with every QoR claim.

  • Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

  • Comparing runs with mismatched constraints or library views.

  • Timing-only fixes that violate power or area budgets.

  • Skipping equivalence checks after structural changes.