Synthesis & Logic Optimization · All levels
Equivalence Hooks: Review Checklist
Review Checklist for Equivalence Hooks.
Review checklist
Review Checklist for Equivalence Hooks focuses on LEC pass rate, unresolved points, debug turnaround. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.
Run manifest is attached (RTL/SDC/libs/switches).
Primary metric and impacted lane are named.
Mechanism hypothesis is evidence-backed.
Fix is reversible and owner-assigned.
Regression matrix includes timing, area, power, and equivalence as needed.
Owners signed: formal owner, synthesis owner, CAD owner.
Sign-off ownership
OWNERSHIP MAP — Equivalence Hooks
artifact owner
---------------- -----------------
compile owner formal owner
timing/power owner synthesis owner
cross-team review CAD owner
Every QoR movement needs a named owner before ECO.Synthesis deep dive
Incremental and ECO synthesis protect schedule only with strict regression discipline.
Concept diagram
INCREMENTAL ECO LOOP
identify delta -> localized compile -> patch -> regression -> releaseMetric graph
ECO CYCLE TIME
full compile ███████████
incremental █████Reports and artifacts
incremental reuse
ECO patch list
LEC status
regression matrix
Mini case study
Localized compile cut turnaround 40%, but skipped LEC caused rollback.
Debug branches
Reuse ratio is not enough
Patch locality check
Always include equivalence hooks
Senior review question
Ask: what evidence proves this QoR move is real and stable?
Key takeaways
State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.
Common pitfalls
Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.
Principal synthesis review addendum
Equivalence hooks align synthesis and ECO transformations with formal checking so aggressive optimization remains provably correct.
Metric: LEC pass rate, unresolved points, debug turnaround